CAD & Engineering Infrastructure Lead

Velaura AI, Inc.; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Velaura AI, Inc. seeks a CAD & Engineering Infrastructure Lead to own the engineering platform for silicon development. You will oversee compute infrastructure, EDA ecosystem, RTL-to-GDS release flow, and AI-assisted workflows that power design teams.

You will manage flow release, CI/CD pipelines, multi-vendor EDA tool deployments, licensing, procurement, and vendor strategy, while enabling scalable, secure, and productive engineering across RTL, verification, DFT, physical design, and packaging.

Qualifications

• Understanding ASIC development lifecycle from RTL to tapeout.
• Hands-on experience maintaining RTL-to-GDS flow environments.
• Experience with multi-vendor EDA tool ecosystems.
• Strong scripting and automation skills (Python/Tcl/Bash).

Responsibilities

• Define and drive Velaura’s engineering infrastructure requirements covering compute, storage, job scheduling, security, backup, disaster recovery and cloud in partnership with stakeholders.
• Lead AI adoption across engineering functions including RTL, verification, DFT, physical design, packaging, software, and CAD itself. Identify where AI-assisted workflows create measurable leverage and drive them from pilot to standard practice.
• Own design-flow CI/CD pipelines including orchestration, flow-release qualification, and result/QoR dashboards
• Provide the compute, capacity, and deployment support that functional regressions run on, scaling to thousands of jobs per week; teams own their regression content, triage, and pass/fail criteria, and this role makes sure the infrastructure underneath never becomes the bottleneck.
• Own flow release process end to end: assemble team-owned flow content into qualified releases, regression-test before deployment, and manage versioning, cadence, and rollback — keeping handoffs from RTL through synthesis, place-and-route, and signoff consistent.
• Lead the deployment, and integration of EDA tools across multiple vendors, balancing productivity, quality, flexibility, and cost.
• Own EDA licensing strategy, vendor relationships, procurement, budgets, IP administration, and license compliance.
• Build and operate the platform behind AI-assisted engineering—model access, agentic tooling, compute capacity, and data pipelines—with the security and IP guardrails required to apply AI to proprietary design data safely, measuring productivity impact and retiring what doesn’t pay off.

Skills

Compute infrastructure

EDA tool deployment

CI/CD pipelines

License management

Python scripting

Automation

Stakeholder communication

AI integration

Multi-vendor EDA

Tools

LSF

Slurm

Synopsys

Cadence

Siemens EDA

Job description

Role Overview

We are looking for a CAD & Engineering Infrastructure Lead to build and own the engineering platform behind Velaura's silicon development: the compute infrastructure, EDA ecosystem, integrated RTL-to-GDS release flow, and AI-assisted workflows that every design team depends on. This role owns flow release and qualification, design-flow CI/CD pipelines, multi-vendor EDA tool deployment, and EDA licensing, procurement, and vendor strategy; domain design methodology and flow content stay with the functional teams: RTL, verification, DFT, physical design, and packaging. The ideal candidate is hands‑on setting up and maintaining integrated RTL-to-GDS flow environments, understands engineering compute infrastructure and license management at scale, and has a practical view of where AI creates measurable leverage in chip development. Above all, this is someone who measures success by how productive everyone else is.

Role Overview

We are looking for a CAD & Engineering Infrastructure Lead to build and own the engineering platform behind Velaura's silicon development: the compute infrastructure, EDA ecosystem, integrated RTL-to-GDS release flow, and AI-assisted workflows that every design team depends on. This role owns flow release and qualification, design-flow CI/CD pipelines, multi-vendor EDA tool deployment, and EDA licensing, procurement, and vendor strategy; domain design methodology and flow content stay with the functional teams: RTL, verification, DFT, physical design, and packaging. The ideal candidate is hands‑on setting up and maintaining integrated RTL-to-GDS flow environments, understands engineering compute infrastructure and license management at scale, and has a practical view of where AI creates measurable leverage in chip development. Above all, this is someone who measures success by how productive everyone else is.

Responsibilities

• Define and drive Velaura’s engineering infrastructure requirements covering compute, storage, job scheduling, security, backup, disaster recovery and cloud in partnership with stakeholders.
• Lead AI adoption across engineering functions including RTL, verification, DFT, physical design, packaging, software, and CAD itself. Identify where AI-assisted workflows create measurable leverage and drive them from pilot to standard practice.
• Own design-flow CI/CD pipelines including orchestration, flow-release qualification, and result/QoR dashboards
• Provide the compute, capacity, and deployment support that functional regressions run on, scaling to thousands of jobs per week; teams own their regression content, triage, and pass/fail criteria, and this role makes sure the infrastructure underneath never becomes the bottleneck.
• Own flow release process end to end: assemble team-owned flow content into qualified releases, regression-test before deployment, and manage versioning, cadence, and rollback — keeping handoffs from RTL through synthesis, place-and-route, and signoff consistent.
• Lead the deployment, and integration of EDA tools across multiple vendors, balancing productivity, quality, flexibility, and cost.
• Own EDA licensing strategy, vendor relationships, procurement, budgets, IP administration, and license compliance.
• Build and operate the platform behind AI-assisted engineering—model access, agentic tooling, compute capacity, and data pipelines—with the security and IP guardrails required to apply AI to proprietary design data safely, measuring productivity impact and retiring what doesn’t pay off.

Required Qualifications

• Deep understanding of the complete ASIC development lifecycle, from architecture and RTL through tapeout—enough to be a credible partner to every functional team.
• Experience owning CAD and infrastructure across multiple successful SoC programs.
• Hands-on experience setting up and maintaining an integrated RTL-to-GDS flow environment—tool and version management, foundry and IP collateral integration, and flow release and qualification across concurrent projects.
• Strong understanding of engineering compute infrastructure: distributed scheduling (LSF, Slurm, or equivalent), storage systems, networking, cloud environments, and license management at scale.
• Hands‑on experience with EDA ecosystems from multiple vendors such as Synopsys, Cadence, and Siemens EDA.
• Strong knowledge of version control, CI/CD platforms, and the compute and storage patterns behind high‑volume regression workloads, along with reproducible engineering practices.
• Excellent scripting and automation skills using Python, Tcl, Bash, or similar.
• Experience evaluating and deploying AI‑assisted engineering tools and workflows, with a practical view of where they create leverage in chip development.
• Excellent communication skills and the ability to influence senior technical leaders across disciplines.

Preferred Qualifications

• Experience scaling infrastructure in an early‑stage semiconductor company.
• Experience with advanced technology nodes with leading foundries.
• Experience building or operating agentic AI systems, LLM‑based tooling, or AI‑native design automation.
• Experience supporting chiplet‑based designs or advanced packaging.

$200,000 - $300,000 a year

Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a base salary and very competitive equity compensation, allowing team members to share in the company’s long‑term success.

The base pay listed represents a good faith estimate that the Company reasonably expects to pay for this position at the time of hire. Actual compensation will depend on multiple factors, including the candidate's skills, qualifications, relevant experience, and geographic location.

In addition to base salary and equity compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well‑being and growth of our team.

Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.

Why Velaura?

Velaura is building next‑generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world.

This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry‑defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: [email protected] . This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case‑by‑case basis.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.