Power-Efficient CPU Microarchitecture Lead

AMD; Santa Clara (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

AMD in Santa Clara, CA is seeking an experienced processor designer to analyze and drive power-efficient microarchitecture development for the Core pipeline in the next-generation processor. You will collaborate with RTL, Architecture, Physical Design and Validation teams to optimize power consumption.

You should be highly experienced in microprocessor development and power-aware RTL logic design, with strong FPGA/ASIC tooling knowledge and a track record of timely delivery.

Qualifications

• MS EE/CE/CS plus years of relevant experience preferred.
• Expert level experience in High-Performance Microprocessor Design.
• Strong experience in low power design techniques with industry tools in CPU/GPU or similar complexity.

Responsibilities

• Analyze power consumption of new and existing micro-architectural features.
• Propose and drive development of new features and optimizations for existing logic.
• Analyze power characteristics of workloads to influence microarchitecture decisions.
• Collaborate with RTL team to improve implementation and interpret power analysis results.
• Work with Physical Design to achieve low power with cutting-edge fabrication technologies.
• Collaborate with Design Verification to generate tests for studied functions.
• Validate power consumption in Silicon and provide feedback to the design process.
• Work with tools/AI to develop new analysis tools and workflows.
• Deliver high-quality products on schedule with cross-functional teams.

Skills

High-Performance Design

Low Power Design

Collaboration

Education

MS EE/CE/CS

Tools

Verilog/SystemVerilog

RTL Methodology

Performance Simulators

Python/Ruby

Job description

AMD in Santa Clara, CA is seeking an experienced processor designer to analyze and drive power-efficient microarchitecture development for the Core pipeline in the next-generation processor. You will collaborate with RTL, Architecture, Physical Design and Validation teams to optimize power consumption.

You should be highly experienced in microprocessor development and power-aware RTL logic design, with strong FPGA/ASIC tooling knowledge and a track record of timely delivery.