Physical Design Manager

Normal Computing Corp.; United States; On-site; USD 170,000 - 260,000; Full time

Job summary

Normal Computing Corp. seeks a seasoned Physical Design Manager to oversee the PD team through end-to-end silicon realization, from synthesis and floorplanning to timing signoff and GDSII tapeout.

You will collaborate with RTL, architecture and DFT teams to shape physical feasibility early in the design cycle and drive PPA targets across AI/HPC architectures.

Qualifications

• Seasoned physical design professional with leadership experience.
• Proven track record of leading tapeouts from netlist to signoff.
• Strong collaboration with RTL, architecture and DFT teams.

Responsibilities

• Lead end-to-end physical design flow from synthesis to tapeout.
• Optimize floorplanning, P&R, CTS, STA and signoff checks.
• Drive PD team hiring, planning and mentoring.
• Collaborate on macro placement, pin assignments, and early feasibility.

Skills

Physical design leadership

Tapeout leadership

P&R optimization

CTS/STA expertise

Floorplanning experience

DRC/LVS signoff

Cross-functional collaboration

Team building & hiring

Scripting (TCL/Python)

Power, performance, area (PPA)

Tools

Innovus

IC Compiler II

Tempus

PrimeTime

Calibre

Pegasus

Job description

• As a Physical Design Manager at Normal, leading the team owns the end-to-end silicon realization path, taking complex architectures from synthesis and physical floorplanning all the way through timing signoff and GDSII tapeout
• Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems, you will shape physical feasibility early in the design cycle by working shoulder-to-shoulder with RTL and architecture teams
• You’ll drive the full backend implementation flow—optimizing floorplanning, place-and-route (P&R), clock tree synthesis (CTS), static timing analysis (STA), and physical verification (DRC/LVS) to achieve aggressive power, performance, and area (PPA) targets
• Physical Design Team Hiring & Leadership: Provide leadership of the PD team, including necessary hiring to support the plan, and individual guidance and performance feedback
• Project Planning: Create work estimates and schedule to support an aggressive tapeout plan
• EDA tools acquisition: Specify and help negotiate the appropriate EDA tools to support the physical design methodology
• Design & Floorplan Reviews: Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro placement, pin assignments, and physical feasibility
• Physical Implementation & Flow: Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and place-and-route (P&R)
• Timing Closure & STA: Own static timing analysis (STA), timing constraints creation/validation, and signoff timing closure across all operating corners and modes
• Power, Area, and Signal Integrity: Drive physical optimization for power, performance, and area (PPA), as well as power integrity (IR/EM) and crosstalk analysis
• Physical Signoff & Verification: Execute full chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, ensuring seamless handoff to the foundry
• Tapeout & Post-Silicon Support: Create and execute tapeout checklists, manage final stream-out processes, and support post-silicon physical debugging and bring-up as needed

We are looking for a seasoned engineer and manager who thrives in cross-functional environments and takes pride in tapeout-proven executionThe ideal candidate brings effective team building and leaders, and a meticulous approach to physical signoff, maintains clarity in fast-paced build cycles, and is excited to solve the physical constraints of novel computing architecturesPD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closureManagerial experience: at least 7 years experience in roleCross-Functional Feasibility: Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibilityBackend Debugging Instincts: Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violationsTapeout Track Record: Lead at least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodesExperience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cyclesExperience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration)Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows