Physical Design Manager ( Fusion Compiler )

Quest Global; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Quest Global in Sunnyvale, CA is seeking a Physical Design Technical Manager focused on Fusion Compiler to lead design closure for 5nm+ nodes. You will drive floorplanning, place-and-route, and power/clock distribution while collaborating with cross-functional teams.

The ideal candidate brings 10+ years in physical design, strong leadership, and expertise with EDA tools such as DC, Genus, Innovus, ICC2, Primetime, Fusion Compiler, and Calibre. You will mentor juniors and push flow improvements.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering or a related technical field, or equivalent practical experience.
• 10+ years of experience in physical design and cross-functional collaboration.
• Strong knowledge of RTL2GDSII flow and tape-out processes in advanced nodes.

Responsibilities

• Deliver low-power designs using advanced UPF methodologies and tight timing closure.
• Lead SoC floorplanning, place & route, and power/clock distribution for high-frequency designs.
• Mentor and lead junior team members and collaborate with cross-functional teams for design closure and signoff.

Skills

Physical design

Timing closure

SoC floorplanning

Power distribution

Clock distribution

UPF techniques

Scripting (TCL/Python)

Interpersonal skills

Education

Bachelor's degree in CS/CE or related field

Tools

DC/Genus

Innovus/ICC2

Primetime

Fusion Compiler

Redhawk/Voltus

Calibre

Job description

Title :: Physical Design Technical Manager ( Fusion Compiler )

Work Experience

What You will Do

• Deliver low power designs using advanced UPF methodologies on 5nm/3nm nodes
• Resolve SoC/SS integration challenges including SDC constraints and UPF promotion/pushdown
• Develop and maintain automation flows using Tcl, Python, and Shell
• Collaborate with cross-functional teams for design closure and signoff
• Mentor and lead junior team members
• Innovate and contribute to flow/methodology improvements

What You Will Bring:

• Experience in physical design and timing closure
• Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• Knowledge of RTL2GDSII flow and design tape-outs in 5nm or below process technologies
• Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Fusion Compiler, Redhawk/Voltus, or Calibre
• Hands-on experience in SoC floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs
• Knowledge of geometry/process/device technology implications on physical design
• 10+ years of experience in interpersonal, teamwork, and demonstrated experience communicating and interfacing with cross-functional teams, IP, and EDA vendors
• Programming/scripting skills: TCL, Python, Perl or Shell