GPU PD Engineer (Austin/San Diego)

Qualcomm; San Diego (CA); On-site; USD 183,000 - 306,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a senior physical design engineer to drive RTL-to-GDS flows for advanced GPU blocks. You will optimize floorplanning, placement, clocking and routing for deep-sub-micron designs, collaborating with RTL and architecture teams to improve power, performance, and area.

The ideal candidate brings extensive experience with Fusion Compiler, ICC2, Genus/Innovus, and Scripting, and can lead complex design flows while mentoring teams across disciplines.

Qualifications

• Experience in physical design implementation including floorplanning, placement, clocking, and routing for complex high-frequency designs.
• Proficiency with physical synthesis and implementation tools and timing/reliability analysis.
• Strong RTL/HDL understanding and ability to optimize PPA while meeting tape-out targets.

Responsibilities

• Lead physical design activities from RTL2GDS flow for state-of-the-art GPUs.
• Collaborate with RTL, architecture and tool vendors to optimize power and performance.
• Develop and improve design flows and methodologies for complex, deep-sub-micron designs.

Skills

Physical design

Floorplanning

Placement

Clock implementation

Routing

Synthesis

Verilog/SystemVerilog

Power, performance, and area (PPA)

Scripting (tcl/perl/python)

Team collaboration

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s degree in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler

ICC2

Cadence Genus/Innovus

Job description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > GPU ASICS Engineering

General Summary:

This role involves the physical implementation of industry-leading integrated graphics core designs, from RTL to GDS, focusing on highly complex and high-frequency blocks or top-level designs. As a senior individual contributor, the candidate will utilize his/her proficiency in industry-standard tools and advanced technology nodes to enhance the Power, Performance, and Area (PPA) metrics of our continuously evolving GPUs. The objective is to optimize designs to meet stringent PPA targets. The candidate will work closely with RTL design and architecture teams to drive and devise innovative solutions for design optimization. The candidate will also work closely with multidisciplinary teams and tool vendors to develop and improve automation in design flows and methodologies, enhancing efficiency. This position demands a comprehensive understanding of the trade-offs in Power, Performance, and Area (PPA) to make informed decisions that achieve optimal design solutions.

The ideal candidate will have/demonstrate the following:

• Experience in Physical design implementation which includes floor-planning, placement, clock implementation, routing for complex, high frequency designs
• Experience with physical synthesis and implementation tools - Synopsys Fusion Compiler, ICC2 and Cadence Genus/Innovus
• Must have good working knowledge of static timing analysis, reliability and power analysis and PDN network
• Strong understanding of CMOS stdcell and memory circuits and design techniques to push Power, Performance and Area of complex designs
• Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks
• Strong understanding of GPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance
• Proven track record of innovation, with the ability to independently tackle and resolve complex technical challenges
• Solid working knowledge of scripting skills including tcl, perl or python
• Excellent communication skills and collaborating in a team environment is a must
• Proven track record of collaborating with diverse teams to drive and resolve complex technical challenges.
• Clock, power delivery network design, process technology, prior experience in flow and methodology development, block closure leading to successful tape-outs
• Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff
• Hands on experience working with very complex designs that push the envelope of Power, Performance and Area
• Hands on experience working with sub-micron technology process nodes eg. 4nm and below is highly advantageous
• Prior experience in flow and methodology development is an advantage
• Demonstrated history of successful innovation with notable accomplishments
• Proficiency in reading and understanding RTL (Verilog/System Verilog)
• Possess excellent debugging and analytical skills, coupled with strong leadership abilities to drive solutions among various teams
• Self-motivated, excellent time management, and strong organizational skills
• Ability to work well in a collaborative environment with multi-disciplined teams

Minimum Skills:

• Bachelor’s degree in Electrical/Computer Engineering
• 17+ years of direct synthesis and physical design work experience

Preferred Skills:

• Master’s degree in Electrical/Computer Engineering
• 15+ years of direct synthesis and physical design implementation work experience
• In depth end to end experience from RTL2GDS, taping out at multiple complex designs in deep sub-micron technology nodes

Minimum Qualifications:

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 6+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 5+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.

Equal Opportunity Statement:

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability‑[e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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EEO Employer:

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Compliance Statement:

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits:

$203,700.00 - $305,500.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.