Engineer-Staff

Nutanix; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Annual discretionary bonus

Annual RSU grants

Competitive benefits

Job summary

Qualcomm Technologies, Inc. seeks a seasoned engineer with 5–10 years of hands-on experience in Synthesis, Place and Route (PnR) and Physical Design to optimize PPA across the design flow.

You will work across synthesis and PD boundary to enhance timing, power, and area in multi-clock domain designs. Ideal candidates have node-traction expertise, strong scripting skills, and familiarity with Innovus/ICC2 and Fusion Genus flows, delivering robust QoR and close collaboration with leadership across

Qualifications

• Bachelor’s degree in Science, Engineering, or related field with 4+ years of ASIC design experience.
• Master’s/PhD with 3+ years is also acceptable.
• Experience with timing closure, synthesis, and PD flows required.

Responsibilities

• Drive end-to-end PPA optimization across synthesis and physical design.
• Manage multi-patterning, CTS, routing, and timing constraints across MCMM designs.
• Collaborate across PD and EDA tools to balance area, power, and performance.

Skills

Python/Tcl

AI usage

Version control

Education

Bachelor’s degree in Science/Engineering

Master’s degree in Science/Engineering

PhD in Science/Engineering

Tools

Innovus

ICC2

Fusion Compiler

Genus

Primetime/ Tempus

Job description

Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:Experience: 5 to 10 years of hands-on experience in Synthesis, Place and Route (PnR), Physical Design, and Timing/Power Signoff.Job Role - Should have strong understanding and in-depth knowledge of Physical Synthesis, and methodologies, Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, with leading industry standard tools — able to work across the synthesis-to-PnR boundary to drive end-to-end PPA optimization rather than treat it as a handoff. - Hands-on experience on advanced technology nodes, including node-specific challenges around double/multi-patterning, pin access, cell legalization, and advanced DRC rules. - Experience with writing and tuning timing constraints for synthesis, STA, timing closure, and pipelining at different levels for performance optimization — and carrying that intent cleanly through to physical closure. - Primary focus on driving PPA activities: aggressive area recovery, leakage/dynamic power reduction, and Fmax/performance pushes, balancing trade-offs across synthesis QoR and physical implementation. - Experience in all aspects of timing closure for multi-clock domain, multi-corner multi-mode (MCMM) designs, both at synthesis and at the physical design stage. - Should have good understanding of low-power design implementation using UPF, including power gating, multi-voltage domains, and level shifter/isolation cell placement/routing. - Experience with different power optimization flows/techniques across synthesis and PD — such as clock gating, cell sizing, Vt swapping, and buffer/inverter insertion/optimization.Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.ORMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.ORPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.Preferred Qualifications:• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.• 6+ years of ASIC design, verification, validation, integration, or related work experience.• 2 + years of experience with architecture and design tools .• 2 + years of experience with scripting tools and programming languages .• 2 + years of experience with design verification methods.• 1 + year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).Skill Set - Proficiency in Python/Tcl and AI Usage. Familiarity with standard software engineering practices like Version Control, Configuration Management, and Regression. - Familiar with PnR tools (Innovus/ICC2) and Synthesis tools (Fusion Compiler/Genus), with the ability to move fluidly between both to close PPA. - Proven hands-on experience on advanced nodes , with awareness of node-specific PPA levers and physical constraints. - Fair knowledge of Static Timing Analysis (PrimeTime/Tempus), LEC, and Low Power (LP) signoff tools. - Proficient in VLSI front-end and back-end design steps — Synthesis, QoR optimization, floorplanning, placement, CTS, routing, and Equivalence Checking. - Strong PPA mindset — comfortable owning power, performance, and area metrics as primary KPIs. -Knowledge of computer architecture and experience in high-speed, low-power processor design will be a plus.Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.Pay range and Other Compensation & Benefits :$140,000.00 - $210,000.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link .If you would like more information about this role, please contact Qualcomm Careers .