Physical Design Engineer, Reality Labs Silicon

Meta; Redmond (WA); On-site; USD 146,000 - 209,000; Full time

Job summary

Meta's Silicon Engineering team is seeking a Physical Design Engineer to translate RTL designs into optimized silicon implementations for VR/AR devices, spanning floorplanning, CTS, routing, and sign-off.

You will collaborate with architecture, RTL, design verification, and DFT teams to ensure high-performance, power-efficient chips and robust physical design flows across advanced nodes. This role is based in Redmond, WA.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience.
• 6+ years of experience in physical design of complex digital ASICs or SoCs, including floorplanning, placement, CTS, routing, and sign-off.
• 6+ years of experience with static timing analysis and timing closure in advanced process nodes (7nm or below).
• Experience with industry-standard physical design EDA tools such as Cadence Innovus, Synopsys ICC2, or equivalent.
• Experience with physical verification flows including DRC, LVS, and antenna sign-off.
• Experience with power analysis and power delivery network implementation, including IR drop and electromigration analysis.

Responsibilities

• Lead physical implementation of complex blocks and subsystems from floorplanning through tapeout, including placement, clock tree synthesis, routing, and physical verification
• Define and drive physical design methodology, constraints, and flows to meet power, performance, and area targets for custom silicon in VR and AR products
• Perform static timing analysis and timing closure across multiple process corners and operating conditions
• Develop and optimize power delivery network strategies, including IR drop analysis and electromigration sign-off
• Collaborate with RTL designers and architects to provide physical design feedback that influences microarchitecture and floorplan decisions
• Partner with design verification and DFT teams to ensure physical implementation supports functional correctness and testability requirements
• Drive physical verification sign-off including DRC, LVS, and antenna checks in advanced process nodes
• Identify and resolve physical implementation bottlenecks related to congestion, timing, and power through iterative analysis and targeted optimization
• Contribute to the development and continuous improvement of internal physical design flows, scripts, and automation to increase team efficiency

Skills

Static timing analysis

Power delivery networks

RTL collaboration

Signal integrity awareness

Education

Bachelor's degree in Computer Science, Computer Engineering, or equivalent

Tools

Cadence Innovus

Synopsys ICC2

Fusion Compiler

FusionPilot/ConfigAI

StarRC

PrimeTime

Job description

Summary:

Meta's Silicon Engineering team is building custom silicon to power the next generation of virtual and augmented reality products, including VR headsets and AR glasses. As a Physical Design Engineer, you will translate RTL designs into optimized silicon implementations, working across floorplanning, placement, clock tree synthesis, routing, and signoff to deliver high-performance, power-efficient chips. In this role, you will collaborate closely with architecture, design, and verification teams to shape the physical implementation strategy for wearable and spatial computing devices that define the future of human connection.

Required Skills:

Physical Design Engineer, Reality Labs Silicon Responsibilities:

1. Lead physical implementation of complex blocks and subsystems from floorplanning through tapeout, including placement, clock tree synthesis, routing, and physical verification

2. Define and drive physical design methodology, constraints, and flows to meet power, performance, and area targets for custom silicon in VR and AR products

3. Perform static timing analysis and timing closure across multiple process corners and operating conditions

4. Develop and optimize power delivery network strategies, including IR drop analysis and electromigration sign-off

5. Collaborate with RTL designers and architects to provide physical design feedback that influences microarchitecture and floorplan decisions

6. Partner with design verification and DFT teams to ensure physical implementation supports functional correctness and testability requirements

7. Drive physical verification sign-off including DRC, LVS, and antenna checks in advanced process nodes

8. Identify and resolve physical implementation bottlenecks related to congestion, timing, and power through iterative analysis and targeted optimization

9. Contribute to the development and continuous improvement of internal physical design flows, scripts, and automation to increase team efficiency

Minimum Qualifications:

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

2. 6+ years of experience in physical design of complex digital ASICs or SoCs, including floorplanning, placement, CTS, routing, and sign-off

3. 6+ years of experience with static timing analysis and timing closure in advanced process nodes (7nm or below)

4. Experience with industry-standard physical design EDA tools such as Cadence Innovus, Synopsys ICC2, or equivalent

5. Experience with physical verification flows including DRC, LVS, and antenna sign-off

6. Experience with power analysis and power delivery network implementation, including IR drop and electromigration analysis

Preferred Qualifications:

Preferred Qualifications:

1. Experience with physical design implementation tools such as Synopsys Fusion Compiler (including FusionPilot/ConfigAI for run analysis and TCL configuration), Cadence Innovus, StarRC, and PrimeTime

2. Experience with physical design for low-power wearable or mobile SoCs, including multi-voltage domain and power gating implementation

3. Experience developing and maintaining physical design automation scripts using Python or Tcl to improve implementation flows

4. Familiarity with co-design methodologies that bridge RTL microarchitecture decisions and physical implementation constraints

5. Experience with advanced node process design kits (5nm or below) and associated physical design challenges

Public Compensation:

$146,000/year to $209,000/year + bonus + equity + benefits

Industry:

Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and affirmatively action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].