Silicon Performance Architect, Reality Labs

Meta; Austin (TX); Presencial; USD 178.000 - 250.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Bonus

Equity

Benefits

Descripción de la vacante

Meta Reality Labs in Austin, TX seeks a Silicon Performance Architect to lead performance modeling, workload profiling, and HW-SW co-design efforts for advanced AI-enabled wearables. You will model IP and DRAM, analyze workloads, and guide architecture decisions with cross-functional teams.

The role requires 8+ years in performance modeling using C/C++ or SystemC, strong SoC/NoC knowledge, Python scripting, and a background in power trade-offs.

Formación

• Bachelor's degree in CS/CE or equivalent practical experience.
• 8+ years creating performance models with C/C++ or SystemC.
• Experience with SoC architecture, NoCs, QoS, memory sub-system.
• Python scripting, automation, and visualization.
• Understanding power concepts and trade-offs.
• Ability to document analyses for cross-functional teams.

Responsabilidades

• Conduct bottleneck analysis of existing and future SoCs to identify improvements.
• Develop accurate models of IP components, SoC fabric, and DRAM to predict performance.
• Analyze workloads and create micro-benchmarks to evaluate performance.
• Identify optimization opportunities and collaborate on HW-SW co-design.
• Collaborate across disciplines, vendors, brainstorm ideas and coordinate multiple initiatives.

Conocimientos

Performance modelling

C/C++

SystemC

SoC architecture

Python scripting

Power optimization

Data analysis

HW-SW co-design

Bottleneck analysis

Educación

Bachelor's degree in CS/CE

MS in EE/CS

Herramientas

RTL verification

Descripción del empleo

Summary:

Reality Labs focuses on delivering Meta's vision through creating advanced AI-enabled wearables. The compute performance and power efficiency requirements of wearables require custom silicon. The custom silicon team within Reality Labs is driving the state-of-the-art forward with breakthrough work in AI, augmented reality, computer vision, machine learning, graphics, displays, and sensors. Our chips will enable wearable devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.As an architect on the the SoC Performance team within Reality Labs, you will play a key role in leading performance modeling, correlation, workload profiling, and analysis efforts.

Required Skills:

Silicon Performance Architect, Reality Labs Responsibilities:

1. Conduct thorough bottleneck analysis of existing and future SoCs to identify areas for improvement
2. Develop accurate models of IP components, SoC fabric, and DRAM to predict performance and inform design decisions
3. Analyze system usage behavior of workloads and create micro-benchmarks to evaluate performance
4. Identify opportunities for optimization and collaborate with hardware teams to solidify HW-SW co-design
5. Work across disciplines, collaborate with vendors, brainstorm ideas and solutions, develop new methodologies, and coordinate multiple initiatives

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
2. 8+ years of experience in creating performance models using C/C++ or SystemC
3. Experience with SoC architecture, NoCs, memory sub-system, Quality of Service (QoS), and heterogeneous compute principles
4. Experience with scripting, infrastructure, automation, and visualization using Python
5. Experience with power concepts and trade-offs
6. Experience deconstructing technical problems, designing performance experiments, analyzing/visualizing data, and sharing detailed analysis in the form of documentation with peers and cross-functional partners

Preferred Qualifications:

1. MS degree in EE/CS or equivalent experience
2. Experience working with cycle-accurate performance models and frameworks for performance architecture evaluations of various SoC components (Accelerators, NoC, DRAM, MMU, etc.)
3. Experience with bare-metal programming, micro-benchmarking, performance instrumentation, Simpoints, etc
4. Experience with RTL design verification
5. Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry:

Internet

Equal Opportunity:

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