Physical Design Engineer III

PRI Global; United States; Remote; USD 100,000 - 140,000; Full time

Job summary

A technology company is seeking a Silicon Physical Design Engineer III for a remote 12-month contract. The successful candidate will develop and manage physical design implementation of low-power designs, resolve physical design issues, and perform power analysis. Candidates should have a Bachelor's degree in Electrical/Computer Engineering/Computer Science and five years of relevant physical design experience. Proficiency in Python, TCL, and Perl is required. This position offers a mid-senior level role in a dynamic technology industry.

Qualifications

• 5 years of relevant physical design experience.
• Experience with physical‑aware logic synthesis and low‑power designs.
• Knowledge of static timing analysis and defining timing constraints.
• Experience in chip power analysis.
• Experience with clock tree synthesis and clock power reduction techniques.

Responsibilities

• Develop physical design implementation of multi‑hierarchy low‑power designs.
• Resolve design and flow issues related to physical design.
• Perform power analysis based on netlist.

Skills

Physical design experience

Python Programming

TCL Programming

Perl Programming

Education

Bachelor’s degree in Electrical/Computer Engineering or Computer Science

Master’s Degree preferred

Job description

Silicon Physical Design Engineer III

Remote • 12 month contract

Responsibilities

• Develop and own physical design implementation of multi‑hierarchy low‑power designs including physical‑aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
• Perform power analysis based on netlist.

Must Have Qualifications

• 5 years of relevant physical design experience.
• Experience with physical‑aware logic synthesis and achieving optimal synthesis QoR on low‑power designs.
• Knowledge of static timing analysis, defining timing constraints and exceptions, corners/voltage definitions.
• Experience in chip power analysis.
• Experience with custom or regular clock tree synthesis implementation at block or top level, and clock power reduction techniques.
• Proficiency in Python, TCL, Perl programming.

Preferred / Nice to Have

• MSEE/CS or equivalent experience.

Education

• Bachelor’s degree in Electrical/Computer Engineering or Computer Science (required).
• Master’s Degree preferred but not required.

Other Information

• Seniority level: Mid‑Senior.
• Employment type: Contract.
• Job function: Other.
• Industries: Technology, Information and Media.