Physical Design Engineer

Value Innovation Labs Inc.; Sunnyvale (CA); On-site; USD 170,000 - 230,000; Full time

Job summary

Value Innovation Labs Inc. in Sunnyvale, CA is seeking an experienced Physical Design Engineer - 3DIC to own the RTL-to-GDSII flow and drive end-to-end ASIC/SoC physical design efforts for advanced nodes.

You will perform synthesis, floorplanning, placement, routing, and CTS while coordinating with IP teams and foundry partners. Requirements include 5–10 years of hands-on design experience, multiple full tape-outs at 5nm/3nm/2nm, MMMC and 3D packaging knowledge, and mandatory Tcl scripting with

Qualifications

• 5–10 years of hands-on ASIC/SoC physical design experience.
• Multiple full-cycle tape-outs at advanced nodes (5nm, 3nm or 2nm).
• Expertise in MMMC, signal integrity, timing closure and 3D packaging.
• Tcl scripting is mandatory; Python or Perl experience is a plus.

Responsibilities

• Own RTL-to-GDSII physical design flow end-to-end.
• Perform synthesis, floorplanning, placement, routing, and CTS.
• Support 3D-IC integration, heterogeneous integration, multi-die assemblies, and TSV planning.
• Drive timing closure, STA, IR drop, and EM analysis.
• Develop and optimize automation scripts using Tcl, Python, or Perl.
• Collaborate with IP teams and foundry partners on advanced-node designs.

Skills

RTL-to-GDSII flow

Synthesis

Floorplanning

Placement

Routing

CTS (Clock Tree Synthesis)

3D-IC integration

TSV planning

Timing closure

STA

EM analysis

Tcl scripting

Python/Perl

Tools

Cadence Innovus

Cadence Tempus

Cadence Voltus

Synopsys ICC2

Synopsys PrimeTime

Job description

We're Hiring: Physical Design Engineer - 3DIC

We are looking for an experienced Physical Design Engineer - 3DIC

• Own the end-to-end RTL-to-GDSII physical design flow.
• Perform synthesis, floorplanning, placement, routing, and Clock Tree Synthesis (CTS).
• Support 3D-IC integration, heterogeneous integration, multi-die assemblies, and TSV planning.
• Drive timing closure, Static Timing Analysis (STA), IR drop, and Electromigration (EM) analysis.
• Develop and optimize automation scripts using Tcl, Python, or Perl.
• Collaborate with IP teams and foundry partners on advanced-node designs.

• 5-10 years of hands-on ASIC/SoC Physical Design experience.
• Experience with multiple full-cycle tape-outs at advanced nodes (5nm, 3nm, or 2nm).
• Strong knowledge of MMMC, signal integrity, timing closure, and 3D packaging technologies.
• Expertise in industry-standard EDA tools such as Cadence Innovus, Tempus, Voltus or Synopsys ICC2, PrimeTime.
• Tcl scripting is mandatory; Python or Perl experience is a plus.

Important: This is a one-time, full-time hiring requirement only. C2C candidates will not be considered.