Physical Design Engineer

Atem Corp; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Atem Corp is seeking a Senior Physical Design Engineer to lead end-to-end physical design activities across multiple California sites (San Jose, San Diego, Irvine). The role requires 12+ years of hands-on ASIC/SoC PD experience, a BS in Electrical/Electronics Eng, and deep expertise with Cadence Innovus and RTL-to-tape-out flows.

Strong scripting and cross-functional collaboration are essential. Based in California, this full-time position involves coordinating with IC Design and RTL teams to

Qualifications

• 12+ years of hands-on experience in physical design of ASIC/SoC.
• Bachelor's Degree in Electrical Engineering, Electronics Engineering, or related field.
• Proficiency with Cadence Innovus and full PD flow from RTL to tape-out.
• Strong TCL and/or PERL scripting skills.
• Excellent communication and collaboration skills.

Responsibilities

• Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.
• Setup and synthesize RTL designs.
• Perform timing closure using various methodologies and strategies, including top-level STA.
• Conduct EM/IR analysis.
• Execute Place & Route (P&R).
• Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.
• Perform floorplanning and layout activities, preferably with top-level floorplanning expertise.
• Contribute to flow and methodology development.
• Collaborate closely with IC Design and RTL Engineering teams.

Education

Bachelor's Degree in Electrical Engineering, Electronics Engineering, or related field

Tools

Cadence Innovus

Job description

• Experience: 12+ Years

• Role: Physical Design Engineer
• Employment Type: Full-Time
• Locations: San Jose, CA / San Diego, CA / Irvine, CA
• Experience: 12+ Years

Key Responsibilities

• Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.
• Setup and synthesize RTL designs.
• Perform timing closure using various methodologies and strategies, including top-level STA.
• Conduct EM/IR analysis.
• Execute Place & Route (P&R).
• Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.
• Perform floorplanning and layout activities, preferably with top-level floorplanning expertise.
• Contribute to flow and methodology development.
• Collaborate closely with IC Design and RTL Engineering teams.

Required Skills

• Strong experience with Cadence Innovus.
• Expertise in the complete Physical Design cycle from RTL to Tape-out.
• Hands-on experience in:
• Synthesis
• Static Timing Analysis (STA)
• Timing Closure
• Place & Route
• Clock Tree Synthesis (CTS)
• Floorplanning
• Physical Verification
• EM/IR Analysis

Strong TCL and/or PERL scripting skills. Proficiency with industry-standard EDA tools. Excellent communication and collaboration skills.

Education

• Bachelor's Degree in Electrical Engineering, Electronics Engineering, or related field.

Preferred Profile

• Deep expertise in top-level floorplanning and STA.
• Proven success delivering complex ASIC/SoC designs through tape-out.