Physical Design Engineer

Quest Global; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Quest Global is seeking an experienced Physical Design Engineer to lead floorplanning, power planning, CTS, and routing for cutting-edge nodes. You will write TCL scripts to optimize standard cell placement and clock trees, and collaborate with RTL/DFT teams to ensure STA/IR/EM/LVS/DRC targets are met.

The ideal candidate has 8+ years in physical design, strong Cadence Innovus/Atop experience, Calibre LVS/DRC proficiency, and solid TCL/Python scripting skills.

Qualifications

• 8+ years of experience in physical design for advanced nodes (2nm/3nm/5nm).
• Proficiency in floorplanning, power planning, CTS, and routing with state-of-the-art EDA tools.
• Ability to write TCL scripts for custom/semi-custom standard cells placements and clock tree adjustments.
• Strong knowledge of STA, IR, EM, LVS, and DRC.

Responsibilities

• Collaborate with RTL and DFT teams to meet design specs.
• Debug and resolve physical design issues across floorplanning to routing.
• Develop TCL/Python scripts to automate placement, CTS, and routing tasks.
• Ensure low power and signal integrity targets are met through design optimization.

Skills

Floorplanning

Power planning

Routing

CTS (Clock Tree Synthesis)

STA/IR/EM/LVS/DRC knowledge

TCL scripting

Python scripting

Perl scripting

Debugging

Innovus

Atop

Calibre LVS/DRC

Low power

Signal integrity

RTL/DFT collaboration

Education

MSEE

MSCS

BSEE/BSCS

Tools

Cadence Innovus

Cadence Atop

Calibre LVS/DRC

Job description

Perform physical design of 2nm/3nm/5nm. Be able to come up with floorplan, powerplan, cts and routing of the design using state-of-art EDA tools like Innovus. Work closely with designers and must be able to write TCL script to perform custom/semi-custom standard cells placements/clock tree adjustments/routing to achieve design specs (STA/IR/EM/LVS/DRC). Good timing analysis and CTS knowledge is required.

MSEE/MSCS + 8years (BSEE/BSCS 10+ years)

Expertise in Cadence Innovus/Atop physical design tools

Experience on Calibre LVS/DRC

Low power, signal integrity experience

Work closely with RTL & DFT designers

Strong TCL/Python scripting knowledge required, Perl is a plus.

Good debug skill and be able to work around issues