Physical Design Engineer

Zodiac Solutions, Inc; San Jose (CA); Presencial; USD 110.000 - 170.000; Jornada completa

Descripción de la vacante

Zodiac Solutions, Inc. in San Jose CA / Austin TX onsite is seeking an experienced IC/ASIC Physical Design Engineer to lead place & route, floorplanning, clock-tree synthesis, and STA, collaborating with RTL and implementation teams to achieve high-quality results.

The ideal candidate will have hands-on experience with hierarchical designs, low power techniques, and robust knowledge of physical verification and sign-off processes.

Formación

• Solid experience in place & route flow, clock-tree synthesis, routing, and timing optimizations.
• Experience on hierarchical designs and/or Low Power implementation is an advantage.
• Experience in Synthesis, interfacing with RTL and implementation designers for better QoR.
• Experience in Floorplan design including placement of hard macros and power grid.
• Experience in Static Timing Analysis related activities (constraints development, parasitic extractions, sign-off).
• Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing).

Conocimientos

Place & route flow

Clock-tree synthesis

Hierarchical designs

Low Power implementation

Synthesis

RTL interfacing

Floorplan design

Static Timing Analysis

Physical Verification

Herramientas

DRC/LVS/DFM

Descripción del empleo

Location: San Jose CA / Austin TX (Onsite)

Job Description

• Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations).
• Experience on hierarchical designs and/or Low Power implementation is an advantage.
• Experience on Synthesis, interfacing with RTL and implementation designers to achieve better quality of results.
• Experience on Floorplan design, including placement of hard macros, padring, power grid and custom analog routes.
• Experience on Static Timing Analysis related activities (constraints development, parasitic extractions, sign-off requirements).
• Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing)