Physical Design Engineer

Highbrow Technology Inc; San Jose (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

Highbrow Technology Inc in San Jose, CA is seeking an experienced Physical Design Engineer/Sr. Physical Design Engineer to drive ASIC physical design from floorplanning through timing closure and signoff.

The role collaborates with RTL, STA, DFT, and verification teams to deliver robust GDSII tapes-outs. Candidates should have hands-on experience with Cadence Innovus, floorplanning, placement, CTS, routing, timing closure, STA, DRC/LVS, and power integrity, plus scripting in Tcl/Python for

Qualifications

• Experience in ASIC/SoC Physical Design and RTL-to-GDSII implementation.
• Floorplanning, placement, CTS, routing, and timing closure.
• Cadence Innovus or similar PD tools.
• Understanding of power planning and power integrity.
• STA and timing optimization experience.
• DRC/LVS, LEC, and PD signoff experience.
• Clock tree synthesis and clock optimization.
• Scripting in Tcl, Python, or Perl is a plus.
• Ability to work with RTL, STA, DFT, verification teams.

Responsibilities

Skills

Floorplanning

Placement

CTS

Routing

Timing closure

STA

DRC/LVS

Power planning

Power integrity

Clock tree synthesis

Scripting (Tcl/Python)

Automation

Education

Bachelors in Electrical/Computer Engineering

Masters in Electrical/Computer Engineering

Tools

Cadence Innovus

Job description

Position: Physical Design Engineer / Sr. Physical Design Engineer

We are looking for experienced Physical Design Engineers for San Jose, CA. The ideal candidate will have hands-on experience in ASIC physical design and implementation, from floorplanning through timing closure and physical signoff.

Requirements:

• Experience in ASIC/SoC Physical Design and RTL-to-GDSII implementation.
• Hands-on experience with floorplanning, placement, CTS, routing, and timing closure.
• Experience with industry-standard physical design tools such as Cadence Innovus.
• Strong understanding of power planning, power grid design, and physical implementation methodologies.
• Experience with Static Timing Analysis (STA) and timing optimization.
• Hands-on experience with DRC/LVS, LEC, and physical design signoff.
• Experience with clock tree synthesis (CTS) and clock optimization.
• Knowledge of IR drop, electromigration (EM), and power integrity is a plus.
• Experience with hierarchical physical design is a plus.
• Experience with multiple technology nodes and tape-outs is a plus.
• Familiarity with low-power design techniques such as power gating, multi-Vt, and voltage islands is a plus.
• Scripting/programming experience using Tcl, Perl, Python, or similar languages is a plus.
• Experience in physical design flow development, automation, or methodology improvement is a plus.
• Ability to work closely with RTL, STA, DFT, verification, and other cross-functional teams.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Relevant experience in ASIC/SoC Physical Design.
• Strong problem-solving and debugging skills.
• Good understanding of the physical design flow from netlist to GDSII.
• Excellent communication and teamwork skills.