Senior Physical Design Engineer

ALTEN; Santa Clara (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

ALTEN is seeking a candidate for SOC Physical Design implementation in Santa Clara, California. The role involves driving SOC physical design through synthesis, DFT insertion, and timing closure, as well as collaboration with Synopsys teams and customers.

The ideal candidate will have strong experience with Synopsys EDA tools and proven execution in delivering high-quality tape-outs. Responsibilities also include developing methodologies and maintaining flows for customer Physical Design Implementation teams.

Qualifications

• Experience with Synopsys Fusion Compiler/ICC2.
• Proficiency in Synopsys Design Compiler.
• Knowledge in SOC implementation methodologies.

Responsibilities

• Drive SOC physical design implementation.
• Develop and maintain Synopsys Flow for customer teams.
• Ensure timing closure and sign-off for SOC designs.

Skills

Synopsys Fusion Compiler/ICC2

Synopsys Design Compiler

RTL to GDS hand-over

SOC clocking methodologies

DFT experience

Ansys Redhawk SC

Physical Verification (PV)

Job description

Overview

Responsible for all aspects of SOC Physical Design implementation. The candidate will represent Synopsys in our Design Services organization and work on physical design implementation for SOC programs contracted to Synopsys. Some projects involve collaboration with Synopsys team members, while others may be customer-augmentation with well-defined responsibilities. Ideal candidates should be highly proficient in using all Synopsys EDA tools and flows without a significant ramp-up, enabling an immediate impact.

Key Responsibilities

• Drive SOC physical design implementation, including synthesis, DFT insertion, place and route, chip finishing, timing closure, and sign-off.

• Develop and maintain Synopsys Flow, methodologies, and constraints for use by customer Physical Design Implementation teams.

Qualifications

• Experience with Synopsys Fusion Compiler/ICC2 (synthesis, DFT insertion, place and route, chip finishing, PT-SI STA, timing closure, PV).
• Proficiency in Synopsys Design Compiler (DC, DCG, DC TOPO).
• Knowledge of Synopsys Flow Development and SOC implementation methodologies for customer teams.
• Familiarity with Synopsys Lynx a plus.
• RTL hand‑over experience for RTL to GDS a plus.
• Top-level floorplanning, bump-maps, RDL IO pad/ring creation/verification, power grid creation/verification, hierarchical floorplanning/partitioning.
• Full SOC clocking methodologies (H-Tree, structure clocking, MS-CTS for top/blocks with push/down and bottom-up approaches).
• Strong SDC/STA constraints development driving back-end tools for block and full-chip timing closure and sign-off.
• Ability to define sign-off requirements and margins based on foundry technology requirements a plus.
• DFT experience with compression, scan, TDF, and MEMBIST a plus.
• Synopsys Formality for formal verification (RTL-to-Gate, Gate-to-Gate) and Formality ECO flows.
• Familiarity with UPF flows and methodologies for multi-voltage power domains with turn-on/turn-off using UPF.
• Synopsys ICV for PV (Physical Verification - DRC/ERC/LVS/PERC).
• Ansys Redhawk SC for IR analysis (static, dynamic, and EMIR).
• Experience implementing design closure on complex IP sub-systems such as PCIe, USB, MIPI, DDR, and HBM a plus.
• Experience with GlobalFoundries, TSMC, and Samsung technology nodes a plus.
• Solid track record on executing and delivering high-quality tape-outs.

Collaboration

The consultant will work well with cross-functional team members both within Synopsys and with customers to meet their SOC development objectives.