SoC Top-Design Engineer (3nm-5nm RTL-to-GDSII)

Sintegra Inc.; San Francisco (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

An innovative technology company in California is seeking an experienced Chip-Level / SoC-Level Design Engineer to join their team. The successful candidate will work on RTL-to-GDSII designs and contribute to SoC-top projects, utilizing tools like Fusion Compiler and ICC2. Key responsibilities include block-level design, scripting in TCL and Python, and working with multi-power domain designs. Familiarity with lower-node technologies is a strong advantage. This role presents an exciting opportunity to innovate within state-of-the-art engineering environments.

Qualifications

• Expertise in RTL-to-GDSII design processes at both block-level and top-level integration.
• Understanding of lower-node technologies (3nm, 4nm, 5nm) is a strong advantage.

Responsibilities

• Perform block-level and chip-level design from RTL-to-GDSII.
• Utilize the Synopsys Implementation tool suite (Fusion Compiler, ICC2).
• Conduct structural implementation and design with multi-power domains.

Skills

Proficiency with Synopsys Implementation tool suite

Strong scripting skills in TCL

Strong scripting skills in Python

Experience in block-level and chip-level design

Familiarity with multi-power domain design

Tools

Fusion Compiler

ICC2

Job description

An innovative technology company in California is seeking an experienced Chip-Level / SoC-Level Design Engineer to join their team. The successful candidate will work on RTL-to-GDSII designs and contribute to SoC-top projects, utilizing tools like Fusion Compiler and ICC2. Key responsibilities include block-level design, scripting in TCL and Python, and working with multi-power domain designs. Familiarity with lower-node technologies is a strong advantage. This role presents an exciting opportunity to innovate within state-of-the-art engineering environments.