Physical Design Engineer

Mirafra Technologies; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Mirafra Technologies in Austin, TX, is seeking a hands-on Physical Design Engineer to drive end-to-end GPU/SoC implementation. You will own synthesis through signoff, CTS, and timing closure for complex layouts, including low-power considerations and physical verification.

The ideal candidate will excel with industry-standard tools (Synopsys/Cadence) and scripting (Python, Tcl, Shell, Perl), analyze congestion and variability at advanced nodes, and collaborate across global teams to deliver

Qualifications

• Experience in full physical design flows including synthesis, place-and-route, CTS, timing closure, and signoff.
• Proficiency with Synopsys or Cadence tools (ICC2, Fusion Compiler, Innovus, PrimeTime, Tempus, StarRC).
• Physical design implementation for complex GPU or SoC designs with low-power design and DRC/LVS verification.
• Experience with timing analysis and closure methodologies and signal integrity.
• Experience with advanced nodes (≤5nm), congestion, IR drop, and variability considerations.
• Strong scripting ability (Python, Tcl, Shell, Perl) and data-driven problem solving.
• Excellent written and verbal communication skills for documenting designs, methodologies, and best practices.
• Excellent collaboration skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global environment.

Responsibilities

• Strong hands-on experience in full physical design flows, including synthesis, place-and-route, clock tree synthesis (CTS), timing closure, and signoff.
• Strong proficiency with Synopsys or Cadence tools (ICC2/Fusion Compiler or Innovus, PrimeTime/Tempus, StarRC).
• Strong experience in physical design implementation for complex GPU or SoC designs, including low-power design and physical verification (DRC/LVS).
• Experience with timing analysis and closure methodologies, including STA and signal integrity.
• Experience with advanced node design (≤5nm), including congestion, IR drop, and variability considerations.
• Strong proficiency in scripting and automation (Python, Tcl, Shell, Perl)
• Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach
• Excellent written and verbal communication skills for documenting designs, methodologies, and best practices
• Excellent collaboration skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global environment

Skills

Physical design

Synthesis

Place and route

Clock Tree Synthesis

Timing closure

Signoff

Scripting

Python

Tcl

Shell

Perl

Synopsys tools

Cadence tools

ICC2

Fusion Compiler

Innovus

PrimeTime

Tempus

StarRC

Physical verification

DRC/LVS

Timing analysis

IR drop

Congestion

Variability

Low-power design

Tools

ICC2

Fusion Compiler

Innovus

PrimeTime

Tempus

StarRC

Synopsys tools

Cadence tools

Job description

• Strong hands-on experience in full physical design flows, including synthesis, place-and-route, clock tree synthesis (CTS), timing closure, and signoff
• Strong proficiency with Synopsys or Cadence tools (ICC2/Fusion Compiler or Innovus, PrimeTime/Tempus, StarRC)
• Strong experience in physical design implementation for complex GPU or SoC designs, including low-power design and physical verification (DRC/LVS)
• Experience with timing analysis and closure methodologies, including STA and signal integrity
• Experience with advanced node design (≤5nm), including congestion, IR drop, and variability considerations
• Strong proficiency in scripting and automation (Python, Tcl, Shell, Perl)
• Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach
• Excellent written and verbal communication skills for documenting designs, methodologies, and best practices
• Excellent collaboration skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global environment

Preferred Qualifications

• Experience with block-level implementation on complex SoC designs
• Exposure to advanced nodes (≤5nm)
• Exposure to GPU or high-performance compute architectures