ASIC Physical Design Lead

Jobtailor; California (MO); On-site; USD 140,000 - 210,000; Full time

Job summary

Jobtailor seeks an experienced Physical Design Engineer to lead fullchip floorplanning and hierarchical implementation across cutting‑edge nanos. You will collaborate with RTL, DFT, and EDA vendors to optimize performance, power, and die size while advancing signoff methodologies with AI‑assisted tooling.

The role requires hands‑on execution of clock mesh/HTree, floorplanning, power grid planning, and robust timing/power integrity analysis for advanced nodes.

Qualifications

• Bachelor’s Degree in Electrical Engineering with 8+ years of Physical Design experience or Master’s Degree in Electrical Engineering with 6+ years of Physical Design experience, or PhD in Electrical Engineering with 3+ years of Physical Design experience.
• Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.
• Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus.
• Experience working on Fullchip activities; including floor-planning, power-grid planning, partitioning and pin-assignment.
• Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis.
• Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
• Experience with custom clock (H-Tree or Mesh) at chip level.
• Experience with Python and usage of AI tools by giving accurate prompts.

Responsibilities

• Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
• Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
• Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning
• Hands‑on experience with Fullchip clock mesh and Flex‑HTree methods
• RTL‑to‑GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization
• Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements
• Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best‑in‑class design methodology
• Proficiency in low‑power design methodologies using UPF
• Work with Foundry and standard cell IP vendors to define the signoff methodologies and validate/adjust them when you receive feedback from Post‑Silicon Validation teams
• Experience in using AI tools to improve productivity

Skills

Physical Design

RTL2GDSII flow

Floorplanning

Power integrity

Timing closure

Python scripting

AI tools usage

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

PhD in Electrical Engineering

Tools

Innovus

Tempus/Primetime

Redhawk/Voltus

Calibre/Pegasus

Job description

Responsibilities

• Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
• Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
• Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning
• Hands‑on experience with Fullchip clock mesh and Flex‑HTree methods
• RTL‑to‑GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization
• Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements
• Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best‑in‑class design methodology
• Proficiency in low‑power design methodologies using UPF
• Work with Foundry and standard cell IP vendors to define the signoff methodologies and validate/adjust them when you receive feedback from Post‑Silicon Validation teams
• Experience in using AI tools to improve productivity

Requirements

• Bachelor’s Degree in Electrical Engineering with 8+ years of Physical Design experience or Master’s Degree in Electrical Engineering with 6+ years of Physical Design experience, or PhD in Electrical Engineering with 3+ years of Physical Design experience
• Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies
• Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus
• Experience working on Fullchip activities; including floor-planning, power-grid planning, partitioning and pin-assignment
• Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis
• Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions
• Experience with custom clock (H-Tree or Mesh) at chip level
• Experience with Python and usage of AI tools by giving accurate prompts