Lead CPU Performance Architect: Microarchitecture Innovator

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 272,000 - 431,250; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in Santa Clara, CA, seeks a seasoned CPU Performance Architect to advance microarchitectural ideas and drive core performance improvements. The role requires shaping front-end, midcore, and memory subsystem innovations with strong collaboration across teams.

You will model and evaluate candidate improvements, implement effective solutions, and partner with verification teams to ensure feasible designs that meet power and area targets. 16+ years frontline experience is expected.

Qualifications

• Deep understanding of brand new CPU microarchitecture and architecture.
• Proven track record of CPU microarchitectural innovation across Front End/ Midcore/ Memory Subsystem Uarch.
• Experience in performance modeling, debugging, and demonstrating merit of innovative ideas.
• Close collaboration with build and verification teams to implement improvements.

Responsibilities

• Innovating and improving CPU performance through microarchitectural ideas.
• Modeling potential improvements to determine merit and feasibility.
• Implementing solutions and collaborating with build, verification, and post-silicon teams.
• Resolve timing, power, and area issues to achieve flawless implementation.
• Partner with lead microarchitects to meet performance, area, and power targets.
• Advocate for ideas, communicating benefits and drawbacks.

Skills

CPU microarchitecture

Performance modeling

Cross-team collaboration

Microarchitecture leadership

Education

Electrical/Computer Eng

Job description

NVIDIA in Santa Clara, CA, seeks a seasoned CPU Performance Architect to advance microarchitectural ideas and drive core performance improvements. The role requires shaping front-end, midcore, and memory subsystem innovations with strong collaboration across teams.

You will model and evaluate candidate improvements, implement effective solutions, and partner with verification teams to ensure feasible designs that meet power and area targets. 16+ years frontline experience is expected.