Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning

Amazon Inc.; Cupertino (CA); On-site; USD 213,000 - 288,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Restricted stock units (RSUs)

Job summary

Annapurna Labs in Cupertino, USA, is seeking an ASIC Physical Design Methodology Engineer to advance RTL2GDS methodologies for ML accelerator chips in cutting-edge nodes. You will optimize CAD flows for PPA, work with EDA vendors, and collaborate across RTL, PD and DFT teams to deliver high-quality designs.

The role requires strong scripting skills (TCL, Python), leadership in technical initiatives, and a track record in low-power design.

Qualifications

• 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes.
• Bachelor's degree in Electrical Engineering or related field required.
• Knowledge of implementing chips with multiple power islands and power gating.
• Experience leading or developing methodology and scripts for physical synthesis.
• Experience with low power design techniques.
• Experience leading technical initiatives and key deliverables.
• Experience with version control systems and CI/CD pipeline implementation.

Responsibilities

• Define, develop and deploy innovative physical design and verification methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes.
• Drive optimizations in CAD flows/methodologies for Power, Performance and Area improvements.
• Collaborate with EDA tool vendors to evaluate new methods and resolve issues.
• Fine tune cloud infrastructure to improve compute and storage utilization for physical design work.
• Interface with RTL, Physical Design, Package Design and DFT teams to improve methodologies.
• Troubleshoot digital tool flows and deploy scalable solutions.
• Create dashboards and central reports for project tracking and QoR/stats visualization.

Skills

ASIC implementation

Synthesis

STA

Physical design

Version control

CI/CD

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or Ph.D. in Electrical Engineering or related field

Tools

EDA tools

Job description

Description

Annapurna Labs (our organization within Amazon Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

Description

Annapurna Labs (our organization within Amazon Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

Amazon provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries.

Custom SoCs (System on Chip) live at the heart of Amazon Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.

Key job responsibilities

• Define, develop and deploy innovative physical design and verification methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes
• Drive Optimizations in CAD flows/methodologies for PPA and TAT improvements
• Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability.
• Fine tune cloud infrastructure to improve compute and storage utilization for physical design work.
• Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies.
• Be able to independently troubleshoot digital tool flow usage and deploy solutions;
• Fluent in scripting languages such as TCL, Python, etc. and able to build scalable and efficient flows to support parallel design developments
• Create Dashboard and Central reports for project tracking and visualizing QoR/stats

Basic Qualifications

• 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience
• Bachelor's degree in Electrical Engineering or a related field
• Knowledge of implementing chips with multiple power islands and power gating
• Experience leading or solely developing methodology and scripts for physical synthesis
• Experience low power design techniques
• Experience leading technical initiatives and key deliverables
• Experience with version control systems and CI/CD pipeline implementation

Preferred Qualifications

• Master's degree or Ph.D. degree in Electrical Engineering or related field
• Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.

USA, CA, Cupertino - 213,000.00 - 287,500.00 USD annually

USA, TX, Austin - 185,200.00 - 250,000.00 USD annually

Company - Annapurna Labs (U.S.) Inc.

Job ID: A10583678