Packaging & Integration Process Engineer

NOISEFIGURE RESEARCH; Redmond (WA); On-site; USD 105,000 - 150,000; Full time

Job summary

NoiseFigure Research in Redmond is seeking a hands-on Packaging & Integration Process Engineer to lead design, execution, and continual improvement of integration workflows across wafer- and panel-level technologies. The role emphasizes collaboration with R&D, hardware, and manufacturing teams while delivering robust, scalable packaging solutions.

You will develop heterogeneous, flexible, and high-density device integration processes and drive yield improvements through experiments and

Qualifications

• BS or higher in engineering or related field.
• Experience with advanced packaging, FPC, PCB assembly, 2.5D/3D integration.
• Hands-on SMT/BEOL, thinning, lithography, etching, deposition, and assembly.
• Proven ability to design experiments and optimize yield.
• Experience collaborating with R&D, hardware, and manufacturing teams.

Responsibilities

• Perform SMT and BEOL processes.
• Lead lamination, lithography, thinning, etching, deposition, and assembly techniques.
• Develop packaging solutions for heterogeneous, flexible, and high-density integration.
• Oversee internal, external, and hybrid manufacturing workflows to accelerate development.
• Drive yield improvement through experiments and process optimization.
• Collaborate with researchers, hardware and manufacturing teams.
• Hands-on fabrication, identify process issues, and drive improvements.
• Flux dipping, wafer grinding, and wire/die bonding for wafer prep and assembly.

Skills

Semiconductor processes

Lamination

Lithography

Thinning

Etching

Deposition

Wire/die bonding

Process optimization

Cross-team collaboration

Experiment design

Data analysis

Education

Bachelor's degree in engineering

Experience in advanced packaging (2.5D/3D) or FHE

Tools

HFSS

FEA software

Job description

Packaging & Integration Process Engineer

We are seeking a hands-on Integration & Packaging Process Engineer to join our advanced manufacturing team. This role focuses on design, execution, and continuous improvement of integration engineering processes across wafer- and panel-level technologies. The ideal candidate is driven to innovate, solve complex challenges, and enable the next generation of heterogeneous, flexible, and high-density device integration.

Key Responsibilities

• Perform surface-mount technology (SMT) and back-end-of-line (BEOL) processes.
• Design & Execute Processes: Lead integration engineering with emphasis on panel/wafer lamination, adaptive laser direct imaging, projection/contact photolithography, component thinning/planarization, wet/dry etch, and metal deposition.
• Innovate & Develop: Create packaging solutions for heterogeneous, flexible, and stretchable integration of electronic components and devices.
• Workflow Ownership: Design and oversee internal, external, and hybrid manufacturing workflows to accelerate development and scale-up.
• New Methods & Yield Improvement: Contribute to the invention of new processes, close critical technology gaps, and design experiments to improve device performance and yield.
• Cross-Team Collaboration: Partner with researchers, hardware engineers, system integration teams, and external manufacturing partners.
• Hands-On Fabrication: Execute fabrication workflows, identify in-line process issues, propose solutions/workarounds, and drive continuous process improvements.
• Assembly & Preparation Support: Perform flux dipping, wafer grinding, and wire/die bonding processes to ensure high-quality wafer preparation and assembly.

Qualifications

• Strong background in semiconductor or advanced packaging processes (wafer-level or panel-level).
• Hands-on experience with lamination, lithography, thinning, etching, deposition, and assembly techniques.
• Knowledge of flux dipping, wafer grinding, and wire/die bonding processes.
• Proven ability to design experiments, analyze results, and optimize yield.
• Experience collaborating across R&D, hardware, and manufacturing teams.
• Strong problem-solving skills with a mindset for innovation and scalability

Minimum Qualifications

• B.S. or equivalent degree in the field of Mechanical Engineering, Electrical Engineering, Aerospace Engineering, Chemical Engineering, Applied Physics, Material Science, or related field.
• Experience with advanced packaging, flexible printed circuit (FPC), printed circuit board assembly (PCBA), 2.5D/3D integration, and/or related technologies, preferably in consumer, wearable, or ruggedized electronic
• Experience with handling and integration of thinned components, surface mount technologies (SMT), and back end of line (BEOL) technologies including: flux dipping, thinning, grinding, dicing, soldering, eutectic bonding, metal finishing/electrochemical deposition, through silicon via (TSV), flip-chip, wire/die bonding, ball/stud bumping, thermocompression bonding, copper pillar bonding, hybrid bonding, underfill, over molding and/or other encapsulation methods
• Demonstrated successful outcomes in innovating and maturing hardware research, instrumentation, and characterization methods, electrical layout, mechanical design, and data analysis or related areas.
• Experience in the development and use of high-performance electronic materials

Desired Qualifications

• PhD or more degree in the field of Mechanical Engineering, Electrical Engineering, Aerospace Engineering, Chemical Engineering, Applied Physics, Material Science, or a related field
• Experience in the domain of advanced packaging, including FPC, MCM, SiP, 2.5D/3D integration, or Flexible Hybrid Electronics (FHE), or similar technologies
• Working experience with reliability testing and failure analysis tools, including die/ball shear/wire pull testing, X-ray, C-SAM, thermal cycling, and other environmental testing
• 2+ years of experience with wearable technologies and technical soft goods
• Practical experience in hermetic/MEMS packaging processes, thermal management/materials, and injection/transfer molding
• Experience with leveraging Finite Element Analysis (FEA) modeling and simulation to drive design acceleration and prevent product failures
• Experience in System-in-Package (SiP) and/or Multi-Chip Module (MCM) design, manufacturing, and validation
• Experience with signal integrity and power integrity simulation (e.g., HFSS) and validation (high-speed eval)