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Benefits offered by this job
Medical, dental, and vision coverage options
Paid family leave
Robust paid time-off programs
Income protection and retirement plans
Opportunities for career growth in nanotechnology-driven semiconductor design
Job summary
A leading semiconductor company in Boise, Idaho, is seeking a Design Engineer to join their DRAM Design & Technology Co-Optimization team. This role involves developing and optimizing nanoscale DRAM circuit designs, collaborating across teams, and contributing to innovations in memory technology. Candidates should have a Master's in Electrical Engineering or Applied Physics and experience in CMOS design and memory analysis. Comprehensive benefits and career growth opportunities are offered.
Qualifications
Strong knowledge of CMOS circuit design and device physics at the nanoscale.
Familiarity with DRAM process technology and I/O design.
Proficiency in industry-standard simulation tools.
Responsibilities
Develop and evaluate circuit and block-level metrics predictive of product-level PPA.
Optimize nanoscale circuit layout for performance, power, and area efficiency.
Drive innovation in future DRAM generations.
Skills
CMOS circuit design
Device physics
Scripting (Python, Tcl, Perl)
Memory design
Communication skills
Problem-solving skills
Education
Bachelor’s or Master’s in Electrical Engineering or Applied Physics
Tools
Hspice
Finesim
Verilog
Job description
A leading semiconductor company in Boise, Idaho, is seeking a Design Engineer to join their DRAM Design & Technology Co-Optimization team. This role involves developing and optimizing nanoscale DRAM circuit designs, collaborating across teams, and contributing to innovations in memory technology. Candidates should have a Master's in Electrical Engineering or Applied Physics and experience in CMOS design and memory analysis. Comprehensive benefits and career growth opportunities are offered.