Principal/MTS, IO Design Engineering

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 100,000 - 130,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid family leave

Robust paid time-off program

Job summary

1000 Micron Technology, Inc. seeks an experienced MTS IO/Clocking Design Engineer to contribute to our IP Design team. You will innovate and verify high-speed IO and clocking circuits critical to our DRAM memory products.

The ideal candidate should possess a minimum of a Master's degree in Electrical Engineering alongside extensive experience in circuit design and strong communication skills. We offer a comprehensive benefits program, including medical, dental, and vision plans, along with paid time off.

Qualifications

• Minimum MSEE + 10 years or BSEE + 12 years of industry experience with a strong background in high-speed IO circuits.
• Strong understanding of good layout practices for high-speed circuits.

Responsibilities

• Innovate, design, optimize, and verify high-speed IO and clocking circuits.
• Develop accurate modeling, analysis, and simulation methodologies.
• Collaborate with process integration and transistor modeling teams.

Skills

High-speed IO circuit design

Strong communication skills

Ability to multi-task

Silicon validation efforts

Education

MSEE + 10 years or BSEE + 12 years of experience

Tools

Perl

Python

Job description

Micron Technology seeks an MTS IO/Clocking Design Engineer to join our IP Design team and contribute to the development of critical high‑speed IP circuits used across Micron’s DRAM memory products.

Responsibilities

• Innovate, design, optimize and verify high‑speed IO and clocking circuits used in new DRAM products.
• Apply robust high‑speed circuit design techniques and evaluate critical performance, including timing and jitter sensitivity, of the IO and clock data paths at the circuit and full‑chip levels.
• Develop accurate modeling, analysis and simulation methodologies to capture key circuit performance metrics and assess their impact on product specifications at the full‑chip and system levels.
• Work with Product Engineering and SI teams to compare silicon performance with simulation results and support correlation activities.
• Collaborate with process integration and transistor modeling teams on Micron’s next‑generation process node.

Minimum Qualifications

• Minimum MSEE + 10 years or BSEE + 12 years of industry experience with a strong background in designing high‑speed IO interface, timing and clocking circuits, proven silicon successes.
• Ability to supervise layout work and understand good layout practices for high‑speed circuits to minimize parasitic impacts.
• Strong communication skills, able to convey sophisticated technical concepts verbally and in writing.
• Mental agility and ability to multi‑task while working with multiple product types and teams in parallel with silicon validation efforts.

Preferred Qualifications

• Experience in DRAM circuit design.
• Experience in channel modeling and characterization, transceiver noise and timing budget analysis, equalization techniques, SI knowledge.
• Understanding of device physics and basic CMOS processing techniques.
• Demonstrated ability in mentoring and coaching early career engineers.
• Experience with AI/ML usage and fluency in scripting languages such as Perl/Python.

Benefits

• Choice of medical, dental and vision plans in all locations.
• Benefit programs that protect income if unable to work due to illness or injury, paid family leave, robust paid time‑off program and paid holidays.

Equal Opportunity Employer

Micron is an equal opportunity workplace and affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.