Mixed-Signal Verification Intern: Design & Validation

Lever, Inc.; Austin, Northern (TX, KY); Hybrid; USD 45,000 - 56,000; Full time

Job summary

Cirrus Logic in Austin seeks highly motivated interns to join the Mixed-Signal Verification Engineering team for 12–16 weeks, Spring through Fall 2027. You will work closely with digital and analog designers, applications engineers, and manufacturing test teams to ensure robust product performance via pre-silicon verification and post-silicon validation.

This internship offers hands-on experience across verification planning, testbench work, failure analysis, and coverage methods, with a hybrid

Qualifications

• Currently pursuing a MS or PhD in Electrical Engineering or a related field.
• Strong background in HDL languages (Verilog or VHDL).
• Familiarity with HVLs like SystemVerilog/UVM, Vera, or e.
• Solid understanding of digital design fundamentals and verification methodologies.

Responsibilities

• Assist in verification planning and strategy development.
• Support testbench creation, maintenance, and enhancement.
• Contribute to failure analysis, debug, and resolution efforts.
• Help with coverage analysis and population to ensure thorough verification.
• Work on digital/mixed-signal modeling, directed and constraint-random test generation, and verification flow development.

Skills

HDL Verilog

HDL VHDL

SystemVerilog/UVM

Digital design fundamentals

Verification methodologies

Education

MS or PhD in Electrical Engineering

Job description

Cirrus Logic in Austin seeks highly motivated interns to join the Mixed-Signal Verification Engineering team for 12–16 weeks, Spring through Fall 2027. You will work closely with digital and analog designers, applications engineers, and manufacturing test teams to ensure robust product performance via pre-silicon verification and post-silicon validation.

This internship offers hands-on experience across verification planning, testbench work, failure analysis, and coverage methods, with a hybrid