Mixed Signal Logic Design Engineer

Intel Corporation; Hillsboro (OR); Hybrid; USD 164,470 - 232,190; Full time

Job summary

Intel Corporation in Hillsboro, Oregon, seeks a Mixed Signal Logic Design Engineer to develop RTL for mixed-signal IPs and help integrate IP blocks in SoCs.

You will collaborate with analog and digital teams to optimize timing, power, and area while validating RTL tests and addressing issues; requires Verilog/SystemVerilog expertise and strong debugging across analog/digital domains.

Qualifications

• Bachelor's degree + 7+ years or Master's + 4+ years in relevant field.
• Expert-level proficiency in Verilog / SystemVerilog (RTL design).
• Strong digital logic fundamentals and experience integrating analog IP with digital logic.
• Deep knowledge of RTL-to-GDSII flow, STA, and CDC.
• Familiarity with EDA tools; understanding timing, power, and performance trade-offs.
• Knowledge of Power Delivery and Power Management systems (preferred).
• Understanding analog/mixed-signal blocks (ADCs, DACs, PLLs, regulators).
• DFT as it relates to mixed-signal HIP.
• Scripting experience (Perl/TCL/Python).
• Experience with mixed-signal simulation and debugging across analog/digital domains.

Responsibilities

• Develop logic design, RTL coding, and simulation for mixed-signal IPs including cell libraries, functional units, IP blocks, and subsystems.
• Participate in definition of architecture and microarchitecture features of the block.
• Apply strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation.
• Write and optimize mixed-signal logic to meet power, performance, and timing goals.
• Ensure design integrity for physical implementation.
• Review verification plans and implementations to verify design features.
• Resolve and implement corrective measures for failing RTL tests.
• Support SoC customers to ensure high-quality IP block integration.

Skills

Verilog/SystemVerilog

Digital logic fundamentals

Analog/digital integration

RTL-to-GDSII/STA/CDC

EDA tools

Python/TCL/Perl scripting

Mixed-signal debugging

Mixed-signal simulation

Power timing trade-offs

Education

Bachelor's degree in Electrical/CS/ECE

Master's degree in Electrical/CS/ECE

Tools

EDA tools

Job description

## Mixed Signal Logic Design EngineerApplylocations: US, Oregon, Hillsboro: US, Massachusetts, Beaver Brook: US, California, Santa Clara: US, Texas, Austintime type: Full timeposted on: Posted Todayjob requisition id: JR0285536# **Job Details:**## Job Description:**Position Overview**Develops the logic design, register transfer level (RTL) coding, and simulation for mixed-signal IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed.Applies various strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed-signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.Reviews the verification plan and implementation to ensure design features are verified correctly, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block.**Key Responsibilities*** Develop logic design, RTL coding, and simulation for mixed-signal IPs including cell libraries, functional units, IP blocks, and subsystems* Participate in the definition of architecture and microarchitecture features of the block being designed* Apply strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation* Write and optimize mixed-signal logic to meet power, performance, area, and timing goals* Ensure design integrity for physical implementation* Review verification plans and implementation to confirm design features are verified correctly* Resolve and implement corrective measures for failing RTL tests to ensure feature correctness* Support SoC customers to ensure high-quality integration of the IP block**What We're Looking For**To be successful in this role, you should demonstrate the following professional traits:* **Cross-functional collaboration** — ability to work effectively with analog, digital, and physical design teams throughout the design cycle* **Ownership mentality** — capable of independently designing and owning mixed-signal subsystems and IP blocks end-to-end* **Strong debugging instincts** — skilled at identifying and resolving issues across both analog and digital domains with precision and efficiency## **Qualifications:****Minimum Qualifications***You must possess one of the following education and experience combinations to be initially considered for this position:** Bachelor's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field with **7+ years** of industry experience, OR* Master's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field with **4+ years** of industry experience*In addition, all candidates must have:** Expert-level proficiency in Verilog / SystemVerilog (RTL design)* Digital logic fundamentals* Experience integrating analog IP with digital logic* Deep knowledge of RTL-to-GDSII flow, STA, and CDC* Familiarity with EDA tools* Understanding of timing, power, and performance trade-offs**Preferred Qualifications*** Knowledge of Power Delivery and Power Management systems* Solid understanding of analog/mixed-signal blocks such as ADCs, DACs, PLLs, and regulators* DFT as it relates to mixed-signal HIP* Scripting language experience, including Perl, TCL/Tk, or Python* Experience with mixed-signal simulation* Strong debugging skills across analog and digital domains## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:US, Oregon, Hillsboro## Additional Locations:US, California, Santa Clara, US, Massachusetts, Beaver Brook, US, Texas, Austin## Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A## BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \* Job posting details (such as work model, location or time type) are subject to change.