Senior Physical Design Integration Engineer

Intel Corporation; Santa Clara (CA); Hybrid; USD 256,050 - 361,480; Full time

Benefits offered by this job

Competitive pay

Stock bonuses

Health benefits

Retirement plans

Paid vacation

Job summary

A leading technology company in California is seeking a Senior Physical Design Integration Engineer to handle CPU design implementation and optimization. The role demands proven leadership skills and extensive experience in ASIC design, with at least 12 years of relevant work history. Candidates should possess a Bachelor's or Master's in Electrical/Computer Engineering and be adept in tools like Unix/Linux, Perl, and TCL. The position offers a compelling salary range and a hybrid work model to attract top talent.

Qualifications

• 15+ years relevant work experience with a Bachelor's or 12+ years with a Master's.
• Capable of leading a small team and interacting with design teams.
• Experience in ASIC design flows like floor planning, synthesis, and verification.

Responsibilities

• Perform physical design implementation of CPU designs from RTL to GDS.
• Conduct all aspects of CPU physical design flow including synthesis and timing analysis.
• Collaborate with various teams to improve CPU microarchitectures.

Skills

Logic Design

VLSI/ASIC Design

Computer Architecture

Unix/Linux

Perl

TCL

Education

Bachelor's in Electrical/Computer Engineering

Master's in Electrical/Computer Engineering

Job description

# **Welcome!**## .Senior Physical Design Integration Engineer page is loaded## Senior Physical Design Integration Engineerlocations: US, California, Folsom: US, California, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR0281584# **Job Details:**## Job Description:At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers.The Physical Design Integration Engineer performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, lowpower synthesizable CPU. Optimizes CPU design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Responsibilities The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc Responsibilities may also include defining design requirements such as frequency, operating voltages, power, etc. to achieve optimized designs on new technologies, processes and architectures The candidate would be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle and take the key learnings into the next product cycle We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systemsGood leadership and communication skills are necessary due to the nature of the work, size and complexity of the products and the size of the team## **Qualifications:**A successful candidate will have proven experience demonstrating the following skills and behavioral traits: Bachelor's in Electrical/Computer Engineering with 15+ years relevant work experience, or Master's in Electrical/Computer Engineering with 12+ years relevant work experienceThe ideal candidate will be capable of leading a small team as well as interacting with architecture and design teams to improve IP and ultimate product quality and performance Experience in: Logic Design, VLSI/ASIC Design, Computer Architecture Current Industry Experience in one or more ASIC style design flows - floorplanning, clock construction, synthesis, place and route, static timing analysis, layout verification Experience with Unix/Linux, Perl and TCL in order to implement useable, flexible cshell/perl/tcl programs that automate tool/flow methodologies## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:US, California, Folsom## Additional Locations:US, California, Santa Clara## Business group:At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.## BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the .Annual Salary Range for jobs which could be performed in the US: $256,050.00-361,480.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \* Job posting details (such as work model, location or time type) are subject to change.\*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.