Mixed Signal Engineer Intern

Ambarella; United States; On-site; USD 110,000 - 160,000; Full time

Job summary

Ambarella is seeking a candidate to join the Mixed Signal team to design, validate and characterize analog IP blocks for SOC. You will work with senior circuit designers on PLL, DLL, SERDES, high-speed IO and data converters for sub-14nm processes, gaining exposure to a broad range of circuit technologies.

Strong fundamentals in analog IC design and knowledge of digital logic including Verilog are required; MS or PhD in EE with possible consideration for summer interns is expected.

Qualifications

• Strong fundamentals in analog integrated circuit design.
• Knowledge of digital logic design, including Verilog.
• MS or Ph.D. in electrical engineering; summer interns considered.

Responsibilities

• Collaborate with senior designers to design, validate and characterize mixed-signal and analog IP blocks for SOC.
• IP blocks include PLL, DLL, SERDES, high-speed IO and data converters for sub-14nm technologies.
• Gain exposure to a broad range of circuit technologies.

Skills

Analog IC design

Digital logic design

Verilog coding

Communication skills

Lab skills

Signal integrity

Education

MS or PhD in EE

Job description

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Job description

As a member of the Mixed Signal team,the candidate will work with senior circuit designers in the design, validation and characterization of mixed signal and analog IP blocks for SOC. The IPs include PLL, DLL, SERDES, high speed IO and data converters, etc. for sub-14nm technologies. The candidate will have exposure to a broad range of circuit and technologies.

Qualification

• Strong fundamental in analog integrated circuit design
• Good knowledge of digital logic design, including Verilog coding
• Excellent communication skills
• Lab skill is a plus
• Knowledge on signal integrity is a plus
• MS or PH.D. in electrical engineering
• Will also consider summer interns