Mixed-Signal IC Design Intern for Edge AI Vision

VisLab (an Ambarella Inc. company)

Headquarters (KY)

On-site

USD 70,000 - 100,000

Full time

14 days+
Application generator

Don’t send a generic resume — generate a resume and cover letter tailored to this exact role.

Get past ATS filters

Benefits offered by this job

Summer internship considered

Job summary

VisLab (an Ambarella Inc. company) is seeking a member of the Mixed Signal team to design, validate and characterize mixed-signal and analog IP blocks for SOC, including PLL, DLL, SERDES, high-speed IO and data converters.

The role offers exposure to sub-14nm technologies and a broad range of circuit technologies. The candidate should have strong fundamentals in analog IC design, knowledge of Verilog, good communication skills, and lab experience; knowledge of signal integrity is a plus.

Qualifications

  • Strong fundamentals in analog IC design.
  • Knowledge of digital logic design and Verilog.
  • Excellent communication skills.
  • Lab skills are a plus.
  • Knowledge of signal integrity is a plus.

Responsibilities

  • Design, validate and characterize mixed-signal and analog IP blocks for SOC.
  • Exposure to PLL, DLL, SERDES, high-speed IO and data converters in sub-14nm technologies.

Skills

Analog IC design
Verilog
Communication skills
Lab skills
Signal integrity

Education

MS or Ph.D. in Electrical Engineering

Job description

VisLab (an Ambarella Inc. company) is seeking a member of the Mixed Signal team to design, validate and characterize mixed-signal and analog IP blocks for SOC, including PLL, DLL, SERDES, high-speed IO and data converters.

The role offers exposure to sub-14nm technologies and a broad range of circuit technologies. The candidate should have strong fundamentals in analog IC design, knowledge of Verilog, good communication skills, and lab experience; knowledge of signal integrity is a plus.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Mixed Signal Engineer Intern
Mixed Signal Engineer Intern

VisLab (an Ambarella Inc. company) • Headquarters (KY)

On-site
USD 70,000 - 100,000
Summer internship considered
Mixed Signal Engineer Intern — SOC IP Design
Mixed Signal Engineer Intern — SOC IP Design

Ambarella • Washington

On-site
USD 120,000 - 180,000
Mixed Signal Engineer Intern
Mixed Signal Engineer Intern

Ambarella • Washington

On-site
USD 120,000 - 180,000
ASIC Design Engineer Intern
ASIC Design Engineer Intern

VisLab (an Ambarella Inc. company) • Kentucky

On-site
USD 70,000 - 110,000
Edge AI ASIC Design Engineer Intern
Edge AI ASIC Design Engineer Intern

Ambarella • United States

On-site
USD 100,000 - 150,000
Firmware & Vision DSP Intern for Edge AI
Firmware & Vision DSP Intern for Edge AI

Ambarella • Washington

On-site
Staff ASIC Design Engineer: Edge AI SoCs for Vision
Staff ASIC Design Engineer: Edge AI SoCs for Vision

Ambarella, Inc. • United States

On-site
USD 195,000 - 226,000
New-hire RSU grants
Opportunity for annual RSU grants
Highly competitive benefits
DFT Engineer for Edge AI Vision SoCs
DFT Engineer for Edge AI Vision SoCs

Ambarella • Headquarters (WA)

On-site
USD 120,000 - 170,000
AMS Verification Engineer — Mixed-Signal & SerDes (Equity)
AMS Verification Engineer — Mixed-Signal & SerDes (Equity)

OLIX • Austin (TX)

On-site
USD 120,000 - 150,000
Competitive Salary
Meaningful stock options
Proximity Bonus
+1
RTL Design Engineer for AI Accelerator SoC
RTL Design Engineer for AI Accelerator SoC

Mentium Technologies Inc. • Santa Barbara (CA)

On-site
USD 140,000 - 220,000
401(k)
Flexible PTO
Full PPO medical, dental, and vision