Mixed Signal Design Verification Engineer

Chipright; United States; Remote; USD 80,000 - 140,000; Full time

Job summary

A leading company in the design space is seeking a Mixed Signal Design Verification Engineer. This role involves implementing System Verilog models for analog blocks, conducting model vs schematic verification, and working within a UVM environment. The position offers competitive compensation and opportunities to work on groundbreaking projects within the mixed-signal design domain.

Qualifications

• Experience with System Verilog Models and analog block verification.
• Understanding of UVM environment and top-level test cases.
• Familiarity with running regressions in mixed-signal design.

Responsibilities

• Implementation of System Verilog models for analog blocks.
• Model vs schematic verification using System Verilog test benches.
• Running regressions and executing designs in the UVM environment.

Skills

System Verilog

AMS simulations

UVM

Model verification

Tools

VManager

Job description

Mixed Signal Design Verification Engineer

Salary: Very Attractive Rate

Location: N/A

Mixed Signal Design Verification Engineer

• Implementation of System Verilog Models for the Analog blocks
• Model vs Schematic Verification – System Verilog Test bench implementation including assertions
• Understanding of adding connect module at the interaction of schematic and model while running AMS simulations
• Understanding of UVM environment and implementing the Top Level Test cases in the environment
• Running regressions using VManager.

Principal Analog AMS RF Recruitment Specialist