Mixed-Signal Design Verification and Validation Engineer

Broadcom Inc.; San Jose (CA); On-site; USD 119,000 - 190,000; Full time

Job summary

An established industry player is seeking a senior Mixed-Signal Design Verification Engineer to join their innovative team. In this role, you will leverage your extensive experience to work on cutting-edge ASICs for data center connectivity applications. The position offers a competitive salary and a comprehensive benefits package, including medical, dental, and retirement plans. As a self-starter and team player, you will collaborate with diverse teams, driving forward-thinking solutions and ensuring high-quality verification processes. This is a fantastic opportunity to make a significant impact in a dynamic and inclusive environment.

Benefits

Medical Insurance

Dental Insurance

Vision Insurance

401(k) Plan

Equity Awards

Paid Holidays

Sick Leave

Vacation

Employee Assistance Program

Qualifications

• 8+ years in Mixed Signal Design Verification or 6+ years with MSc.
• Hands-on experience with SV UVM and verification coverage matrix.

Responsibilities

• Work on ASICs for data center connectivity applications.
• Develop verification environments for DFT patterns.

Skills

Mixed Signal Design Verification

SV UVM

Regression Tests

Analog Mixed-Signal Knowledge

EDA Tools (Synopsys, Cadence)

GLS Simulations

DFT Design Verification

Memory BIST Controllers

Education

BSc in Electrical Engineering

MSc in Electrical Engineering

Tools

Synopsys

Cadence

Job description

Mixed-Signal Design Verification and Validation Engineer

Apply locations: USA-CA San Jose Plumeria Drive

Time type: Full time

Posted on: Posted 3 Days Ago

Job requisition id: R022861

Job Description:

Broadcom is seeking a senior-level Mixed Signal Design Verification engineer. In this highly visible role, you will work on ASICs for data center connectivity applications.

Qualifications include:

• BSc in Electrical Engineering or Computer Engineering with 8+ years of experience in Mixed Signal Design Verification, or MSc with 6+ years of experience
• Hands-on experience with SV UVM, SV RNM, and verification coverage matrix
• Familiarity with writing regression tests, developing checkers, assertions, and verification plans
• Knowledge of analog mixed-signal building blocks such as ADCs, DACs, PLLs, and SerDes
• Experience generating randomized vectors for analog and digital behavioral model verification
• Proficiency with industry-standard EDA tools like Synopsys and Cadence
• Experience with GLS simulations, with and without parasitic annotations
• Background in verification of DFT design, architecture, and microarchitecture
• Experience developing verification environments for DFT patterns such as Stuck, Transition, MBIST, and Boundary Scan
• Knowledge of Memory BIST controllers with repair features is a plus
• Self-starter and team player

Highly Desired Qualifications:

• Strong communication skills for technical and management levels
• Proactive, collaborative, and innovative approach
• Excellent time management and interpersonal skills

Additional Job Details:

Compensation and Benefits:

The annual base salary ranges from $119,000 to $190,000.

This position may include a discretionary annual bonus, equity awards, and a comprehensive benefits package including medical, dental, vision, 401(k), ESPP, EAP, paid holidays, sick leave, and vacation. The company complies with all relevant laws regarding leaves of absence and family leave.

Equal Opportunity Employer:

Broadcom values diversity and inclusion. We consider all qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability, medical condition, pregnancy, veteran status, or any other protected characteristic. We also consider applicants with arrest and conviction records in accordance with applicable laws.

Note: If located outside the USA, please provide a home address for future correspondence.