Memory Layout Engineer (Germany)

leadIC Design Pvt Ltd; Germany (OH); On-site; USD 69,775 - 93,034; Full time

Job summary

leadIC Design Pvt Ltd is seeking a Memory Layout Engineer with 5–7 years of hands-on experience in memory layout design, mainly on lower technology nodes. The successful candidate will perform layout development, verification, and work closely with design and verification teams.

This role demands expertise in memory layout for SRAM/memory blocks and experience with DRC/LVS closure to ensure compliance with density requirements.

Qualifications

• 5–7 years of experience in memory layout engineering.
• Strong experience in lower technology nodes.
• Hands-on with DRC/LVS closure.
• Good understanding of semiconductor layout fundamentals.

Responsibilities

• Perform memory layout design for SRAM/memory blocks.
• Work on lower technology nodes.
• Ensure layout meets DRC, LVS, and density requirements.
• Optimize layout for performance, power, and area (PPA).
• Collaborate with circuit design and verification teams.
• Support tape-out activities and resolve layout-related issues.

Skills

memory layout engineering

lower nodes

DRC/LVS closure

semiconductor layout fundamentals

Job description

Experience: 5–7 Years

Location: Germany

Domain: Semiconductor / Memory Design

Role Overview

We are looking for a Memory Layout Engineer with 5–7 years of hands‑on experience in memory layout design, specifically on lower technology nodes. The role involves layout development, verification, and close collaboration with design and verification teams.

Key Responsibilities

• Perform memory layout design for SRAM / memory blocks

• Work on lower technology nodes (mandatory)

• Ensure layout meets DRC, LVS, and density requirements

• Optimize layout for performance, power, and area (PPA)

• Collaborate with circuit design and verification teams

• Support tape‑out activities and resolve layout‑related issues

Mandatory Skills

• 5–7 years of experience in memory layout engineering

• Strong experience in lower nodes (mandatory)

• Hands‑on with DRC/LVS closure

• Good understanding of semiconductor layout fundamentals

Good to Have

• Experience with advanced memory architectures
• Exposure to multiple process nodes
• Strong communication and teamwork skills