Memory Layout Engineer
Leadic Design
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Job summary
Leadic Design is seeking a Senior Memory Layout Engineer with over 5 years of SRAM experience and strong knowledge in TSMC FinFET technologies. The role is key to supporting the chip development lifecycle and involves working with advanced tools like Cadence Virtuoso.
Located in Germany, this position offers the opportunity to collaborate with semiconductor companies globally. Applicants should be prepared for a notice period of up to 60 days.
Qualifications
- 5+ years of SRAM Memory Layout experience.
- Expertise in TSMC FinFET (7nm/5nm/3nm/2nm).
- Experience with Cadence Virtuoso XL/EXL/MXL.
Job description
Posted: 6 days ago, Openings: 2, Applicants: Less than 10
Location: Germany
Notice period: Up to 60 days
Senior Memory Layout Engineer with 5+ years of SRAM Memory Layout experience and expertise in TSMC FinFET (7nm/5nm/3nm/2nm) and Cadence Virtuoso XL/EXL/MXL.
Skills highlighted as preferred key skills.
Founded in 2018, LeadIC has evolved into a trusted partner for global semiconductor companies, supporting the complete chip development lifecycle with deep technical capability. Engineering teams are located across India, Germany, and Canada.
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