Memory Design Performance Engineer (SRAM Specialist)

EDA CAREERS, (Technology Futures Inc).; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

EDA CAREERS, (Technology Futures Inc) is seeking a Performance Engineer specializing in SRAM memory design in the Bay Area. This well-funded startup values deep memory architectures, cache coherency, and performance optimization to accelerate high-speed subsystems.

Design and model memory hierarchies in C/C++ for simulation; optimize performance with cache coherency improvements and prefetching strategies. Collaborate across teams to enhance SoC memory subsystems, conduct pre-silicon validation,

Qualifications

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field; Ph.D. preferred.
• Extensive experience in memory design, specifically with SoC architecture and memory subsystems.
• Proficient in programming languages C, C++, Python, and experience with modeling and simulation tools.
• Strong understanding of cache coherency protocols (e.g., CHI, MESI/MOESI) and on-chip interconnects.
• Proven ability to analyze SoC performance regarding bandwidth and latency.

Responsibilities

• Design and model memory architectures and memory hierarchies using C/C++ for simulation.
• Optimize memory performance through cache coherency improvements and prefetching strategies.
• Collaborate with cross-functional teams to enhance system-level cache architectures and interconnect designs.
• Conduct pre-silicon performance modeling and validation to predict and mitigate potential bottlenecks.
• Develop advanced cycle-accurate simulations for memory components and evaluate performance metrics.

Skills

Memory design

C/C++

Python

Modeling & simulation

Cache coherency

Cache coherency protocols

Education

Bachelor's or Master's degree

Ph.D. preferred

Tools

RTL validation

Simulation tools

Job description

EDA CAREERS, (Technology Futures Inc) is seeking a Performance Engineer specializing in SRAM memory design in the Bay Area. This well-funded startup values deep memory architectures, cache coherency, and performance optimization to accelerate high-speed subsystems.

Design and model memory hierarchies in C/C++ for simulation; optimize performance with cache coherency improvements and prefetching strategies. Collaborate across teams to enhance SoC memory subsystems, conduct pre-silicon validation,