Memory Architect: Low-Power Embedded SRAM for SoCs

Qualcomm

San Diego (CA)

On-site

USD 164,000 - 246,000

Full time

14 days+
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Benefits offered by this job

Competitive annual discretionary bonus
Annual RSU grants
Comprehensive benefits package

Job summary

Qualcomm is seeking a talented engineer in San Diego to join the Memory IP team, focusing on designing low-power, high-performance embedded memory circuits. In this role, you’ll collaborate with various teams to ensure top performance of Snapdragon products.

Ideal candidates should have a degree in Science or Engineering with relevant ASIC design experience, alongside familiarity with memory design and physical implementation. Competitive pay range is $164,000 - $246,000, with additional benefits including bonuses and RSUs.

Qualifications

  • 2+ years of academic or professional experience designing embedded memories for SoC applications.
  • Knowledge of CPU L1/L2 cache design, compiler SRAM/Register File architectures.
  • Understanding of high-performance and low-power design features and techniques.

Responsibilities

  • Develop custom digital circuits for high-speed and low-power SRAM designs.
  • Perform schematic capture and simulation of major blocks.
  • Collaborate with the CAD team for full verification.

Skills

Designing embedded memories for SoC applications
CPU L1/L2 cache design
Advanced custom circuit implementations
Variation-aware design in nanometer CMOS
Physical implementation impact on circuit performance

Education

Bachelor's degree in Science or Engineering
Master's degree in Science or Engineering
PhD in Science or Engineering

Job description

Qualcomm is seeking a talented engineer in San Diego to join the Memory IP team, focusing on designing low-power, high-performance embedded memory circuits. In this role, you’ll collaborate with various teams to ensure top performance of Snapdragon products.

Ideal candidates should have a degree in Science or Engineering with relevant ASIC design experience, alongside familiarity with memory design and physical implementation. Competitive pay range is $164,000 - $246,000, with additional benefits including bonuses and RSUs.

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