Lead VLSI Physical Design Engineer – RTL to GDSII

VLSI Worlds; Folsom, Northern (CA, KY); Hybrid; USD 180,000 - 260,000; Full time

Job summary

VLSI Worlds in Folsom, CA is seeking a Senior Physical Design Engineer for ASIC/SoC projects. You will lead block-level physical design from RTL to GDSII, ensuring timing, power, and area targets are met on advanced nodes.

The role requires 10+ years of relevant experience and hands-on Fusion Compiler expertise. You will collaborate with RTL, EDA, and tape-out teams to deliver silicon on schedule.

Qualifications

• Must have 10+ years of experience in ASIC/SoC physical design.
• Proficient with Fusion Compiler for RTL-to-GDSII flow.

Responsibilities

• Lead block-level physical design from RTL to GDSII.

Skills

Experience (10+ yrs)

Tools

Fusion Compiler

Job description

VLSI Worlds in Folsom, CA is seeking a Senior Physical Design Engineer for ASIC/SoC projects. You will lead block-level physical design from RTL to GDSII, ensuring timing, power, and area targets are met on advanced nodes.

The role requires 10+ years of relevant experience and hands-on Fusion Compiler expertise. You will collaborate with RTL, EDA, and tape-out teams to deliver silicon on schedule.