VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS (10+ Yrs)

Dexian; Folsom (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Dexian is seeking a VLSI Physical Design Engineer for an ASIC/SoC project in Folsom, CA. This contract role (3+ months) requires leading block-level physical design from RTL to GDSII and close collaboration with RTL, timing, and floorplanning teams.

Candidate must have 10+ years of experience, hands-on use of advanced nodes, and proficiency with Fusion Compiler to meet timing, area, and power goals in a fast-paced environment.

Qualifications

• 10+ years of experience in VLSI physical design
• Expertise with advanced nodes (e.g., 7nm/5nm) desired
• Experience with RTL-to-GDSII flow and timing closure

Responsibilities

• Lead block-level physical design from RTL to GDSII
• Collaborate with RTL, clock, and floorplanning teams
• Ensure design meets timing, area, and power targets using Fusion Compiler

Skills

Block-level PD leadership

RTL to GDSII expertise

Tools

Fusion Compiler

Job description

VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS

Folsom, CA

3 + Months

Role:
Lead block-level physical design from RTL to GDSII.

Must Have:
10+ years exp, advanced nodes, and Fusion Compiler.

Dexian is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.