Lead Systems Architect - Physical AI & SoC Solutions

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 186,000 - 345,000; Full time

Benefits offered by this job

Bonus & equity

Benefits package

Paid time off

401(k) with employer match

Stock purchase plan

Medical/dental/vision coverage

Job summary

Cadence Design Systems, Inc. is seeking a Systems Solutions Architect and Technical Lead to define compute-centric subsystems for AI applications.

You will shape the SoC architecture using Cadence DSPs, CPUs, NPUs, and accelerators, and partner with RTL and software teams to maximize performance and power efficiency. Responsibilities include owning system architecture, driving simulations with SystemC/TLM, and delivering PoCs that showcase the Cadence IP stack.

Qualifications

• 12+ years in a leading architectural or system engineering role.
• Experience designing integrated hardware-software solutions.
• Experience with SystemC, TLM, or cycle-accurate simulators.
• Experience in Physical AI (robotics, autonomous systems) with real-time imaging/radar and advanced audio.
• Strong written and verbal communication; travel up to 10%.

Responsibilities

• Define and own the system architecture for new hardware subsystems and software stack.
• Architect solutions using the Cadence SSG IP and coordinate with RTL and software teams.
• Partner with Performance Modeling teams to build cycle-accurate simulations.
• Hand off architectural specs to RTL/Hardware and Software/Firmware teams.
• Lead PoC and reference designs to demonstrate Cadence IP capabilities.

Skills

System architecture

Performance modeling

SystemC/TLM simulation

Physical AI expertise

Technical communication

Travel readiness

Tools

SystemC

TLM

Cycle-accurate simulators

Job description

Cadence Design Systems, Inc. is seeking a Systems Solutions Architect and Technical Lead to define compute-centric subsystems for AI applications.

You will shape the SoC architecture using Cadence DSPs, CPUs, NPUs, and accelerators, and partner with RTL and software teams to maximize performance and power efficiency. Responsibilities include owning system architecture, driving simulations with SystemC/TLM, and delivering PoCs that showcase the Cadence IP stack.