Edge AI Systems Architect & Tech Lead

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 186,000 - 345,000; Full time

Job summary

Cadence Design Systems, Inc. is seeking a Systems Solutions Architect and Technical Lead to define compute-centric subsystems for AI applications using Cadence DSPs, CPUs, NPUs, and accelerators.

You will analyze Edge AI and Physical AI requirements and optimize subsystems for power, performance, and software flexibility. You will collaborate with hardware, software, and performance modeling teams, translate architectural specs to RTL and firmware, and build PoC designs that demonstrate the

Qualifications

• 12+ years in architectural or system engineering leadership.
• Experience designing integrated hardware-software solutions.
• Proven ability to run performance modeling teams.
• Experience in Physical AI including real-time imaging or radar and advanced audio processing.

Responsibilities

• Define and own the system architecture for new hardware subsystems (compute, memory, interconnects) and software stack (drivers, HAL, runtimes).
• Architect solutions using Cadence IP across compute, accelerators, interfaces and memory controllers.
• Collaborate with Performance Modeling teams to build cycle-accurate simulations and identify bottlenecks.
• Hand off architectural specs to RTL/Hardware and Software teams ensuring alignment.
• Build PoC and reference designs demonstrating the Cadence IP platform.

Skills

System architecture

Performance modeling

Cross-functional collaboration

Communication skills

Travel readiness

Tools

SystemC

TLM

Cycle-accurate simulators

RTL integration

Job description

Cadence Design Systems, Inc. is seeking a Systems Solutions Architect and Technical Lead to define compute-centric subsystems for AI applications using Cadence DSPs, CPUs, NPUs, and accelerators.

You will analyze Edge AI and Physical AI requirements and optimize subsystems for power, performance, and software flexibility. You will collaborate with hardware, software, and performance modeling teams, translate architectural specs to RTL and firmware, and build PoC designs that demonstrate the