Lead SoC Verification Architect — Hybrid HPC Chip Innovator

Inspire Semiconductor, Inc.; Austin, Northern (TX, KY); Hybrid; USD 140,000 - 210,000; Full time

Benefits offered by this job

Hybrid work model

Fully remote possible for exceptional候

Job summary

Inspire Semiconductor, Inc. seeks a seasoned Lead SoC Verification Engineer to own verification of a high-performance cluster-on-a-chip including RISC-V cores, NoC, and IP integrations. You’ll lead a team, define verification plans, and select tools to ensure robust, high-performance designs.

You will mentor engineers, drive testbench development, and push automation across the verification pipeline, shaping the future of our scalable HPC chips.

Qualifications

• Minimum 7+ years hands-on SoC verification experience.
• Strong SystemVerilog, UVM proficiency and simulation tool expertise.
• Experience in interfacing simulations to software/hardware via DPI/VPI.
• Proficiency with version control and project tracking tools (Git/Bitbucket, Jira/Confluence).
• Solid knowledge of common bus protocols (AXI, AHB, PCIe, DDR4/5).
• Excellent scripting and programming skills (Python, C/C++, TCL).
• Strong communication and collaboration abilities.

Responsibilities

• Craft and execute comprehensive verification plans from the ground up.
• Develop unit- and system-level testbenches.
• Implement and verify RISC-V ISA compliance tests.
• Debug issues in collaboration with design team.
• Improve functional and code coverage, identify bottlenecks.
• Integrate simulations with interfaces, stimulus generators and checkers.
• Drive verification infrastructure, automation, and test framework improvements.
• Mentor and grow a verification engineering team.

Skills

SoC verification

SystemVerilog

UVM

Python

C/C++

TCL

Education

Bachelor’s or Master’s in Electrical or Computer Engineering

Tools

Xcelium

DPI/VPI

Git

Bitbucket

Jira

Confluence

Job description

Inspire Semiconductor, Inc. seeks a seasoned Lead SoC Verification Engineer to own verification of a high-performance cluster-on-a-chip including RISC-V cores, NoC, and IP integrations. You’ll lead a team, define verification plans, and select tools to ensure robust, high-performance designs.

You will mentor engineers, drive testbench development, and push automation across the verification pipeline, shaping the future of our scalable HPC chips.