Lead SoC Architect - Edge AI, High Ownership & Equity

Oho Group; San Francisco (CA); On-site; USD 260,000 - 380,000; Full time

Job summary

The Oho Group, in partnership with a well-funded stealth startup, seeks an experienced Lead SoC Architect to define the overall SoC architecture for a next-generation edge AI device. You will translate product requirements into an actionable technical roadmap and guide implementation through to tapeout.

You will lead cross-functional teams across compute, interconnect, memory and high-speed interfaces, balancing performance, power and thermal constraints while coordinating with an external ASIC

Qualifications

• 10+ years of experience designing complex SoCs.
• Proven track record delivering silicon through successful tapeout.
• Experience writing detailed architecture and design specifications.
• Ability to work across architecture, implementation and external engineering teams to solve complex technical challenges.

Responsibilities

• Define and own the overall SoC architecture for a complex edge AI device.
• Translate product requirements into detailed architectural specifications.
• Lead integration of key SoC subsystems, including compute, interconnect, memory and high-speed interfaces.
• Balance performance, power and thermal requirements through architectural trade-offs.
• Work closely with an external ASIC design partner to ensure successful implementation.
• Review floorplanning, timing closure and physical implementation to maintain architectural goals.

Skills

SoC architecture

Tapeout experience

Cross-functional leadership

Architectural specifications

Job description

The Oho Group, in partnership with a well-funded stealth startup, seeks an experienced Lead SoC Architect to define the overall SoC architecture for a next-generation edge AI device. You will translate product requirements into an actionable technical roadmap and guide implementation through to tapeout.

You will lead cross-functional teams across compute, interconnect, memory and high-speed interfaces, balancing performance, power and thermal constraints while coordinating with an external ASIC