Lead RTL & UVM Verification for Multimedia IPs

Google; San Diego (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Bonus target

Job summary

Google is seeking an experienced verification lead to drive IP- and subsystem-level verification for complex ASICs, including Camera ISP/Multimedia and DVFS features. You will partner with architecture and design teams to ensure robust, scalable verification strategies and efficient tape-out readiness.

The role requires 10+ years in RTL verification, 4+ years of people management, and a strong background in SystemVerilog and UVM.

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CE/CS.
• 10 years of experience verifying digital logic at RTL using SystemVerilog for ASICs.
• 4 years of experience in people management, developing employees.
• Experience constructing reusable verification components and environments using UVM.
• Experience leading verification and validation cycles for subsystems such as Camera ISP/Multimedia, Display, TPU/GP U, processors, or SOC level.

Responsibilities

• Plan and execute IP- and subsystem-level verification for ISP/Multimedia hardware, partnering with architecture and design teams.
• Lead subsystem verification for power and performance, including low-power design and DVFS features.
• Build and enhance SystemVerilog/UVM constrained-random testbenches with engineers to ensure robust blocks.
• Define, measure, and close comprehensive coverage across stimuli and corner cases to reduce holes.
• Mentor a global DV team across methodology, scheduling, regressions, and reviews.

Skills

RTL verification

Leadership

Constrained-random testing

Power/performance verification

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Master's degree or PhD (preferred)

Tools

SystemVerilog

UVM

SystemVerilog Assertions (SVA)

Job description

Google is seeking an experienced verification lead to drive IP- and subsystem-level verification for complex ASICs, including Camera ISP/Multimedia and DVFS features. You will partner with architecture and design teams to ensure robust, scalable verification strategies and efficient tape-out readiness.

The role requires 10+ years in RTL verification, 4+ years of people management, and a strong background in SystemVerilog and UVM.