Lead Reliability Architect – Silicon Photonics & CPO

Ayar Labs; San Jose (CA); On-site; USD 200,000 - 260,000; Full time

Job summary

Ayar Labs in San Jose, CA is seeking a Principal Engineer, Reliability to lead the reliability roadmap for silicon photonics and mixed-signal EICs, bridging R&D and high-volume manufacturing.

You will drive Design for Reliability, CAPA, and WLR programs with foundry and OSAT partners, develop physics-of-failure models, and influence PIC‑EIC integration at the co-packaged optics interface.

Qualifications

• Bachelor’s degree required in a relevant field.
• 10+ years semiconductor reliability experience with emphasis on silicon photonics and mixed-signal EIC reliability.
• Experience with reliability mechanisms: electromigration, HCI, NBTI/PBTI, ESD, latch‑up.
• Deep understanding of foundry process flows and reliability challenges in photonics and CMOS/mixed-signal processes.
• Proven ability to develop aging models (Arrhenius, Coffin–Manson) and PoF modelling.
• Familiarity with JEDEC, Telcordia (GR-468), and MIL‑STD qualification standards.

Responsibilities

• Owns Reliability roadmap and CAPA activities for PIC-EIC products.
• Implements Design for Reliability across photonics chiplet and mixed-signal EIC.
• Leads reliability collaboration with foundries and OSATs for process qualification and packaging.
• Develops PoF models and runs Weibull/Lognormal analyses on ALT data.

Skills

Semiconductor reliability

Silicon photonics

Mixed-signal EIC

FMEA

DFR design

JEDEC/MIL-STD

Python for lab control

Education

Bachelor’s degree in Electrical Engineering/Physics/related

PhD or Master’s (preferred)

Tools

Python

JMP/Minitab

Job description

Ayar Labs in San Jose, CA is seeking a Principal Engineer, Reliability to lead the reliability roadmap for silicon photonics and mixed-signal EICs, bridging R&D and high-volume manufacturing.

You will drive Design for Reliability, CAPA, and WLR programs with foundry and OSAT partners, develop physics-of-failure models, and influence PIC‑EIC integration at the co-packaged optics interface.