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Job summary
A leading technology company in California seeks a Senior Formal Verification Engineer to verify AI-related ASIC designs using formal verification methods. The ideal candidate has over 12 years of experience in ASIC verification, with mastery of SystemVerilog Assertions and proficiency in formal verification tools. The position offers a competitive salary ranging from $196,000 to $310,500, along with equity and benefits, along with a commitment to diversity and equal opportunity in employment.
Qualifications
12+ years in ASIC verification with 8+ years focused on formal verification methods.
Mastery of SystemVerilog Assertions (SVA) and formal property verification.
Proficient in at least one popular formal verification tool in the industry.
Responsibilities
Verify AI-related sophisticated ASIC designs with formal verification methods.
Partner with architecture/RTL teams to specify properties and resolve design issues.
Develop advanced formal verification environments and methodologies.
Skills
SystemVerilog Assertions (SVA)
Formal verification methods
Scripting skills (TCL, Python)
Attention to detail
Good written and oral communication skills
Education
BS/MS/PhD or equivalent experience in CS/CE/EE
Tools
Formal verification tools (JasperGold, VC Formal)
Job description
A leading technology company in California seeks a Senior Formal Verification Engineer to verify AI-related ASIC designs using formal verification methods. The ideal candidate has over 12 years of experience in ASIC verification, with mastery of SystemVerilog Assertions and proficiency in formal verification tools. The position offers a competitive salary ranging from $196,000 to $310,500, along with equity and benefits, along with a commitment to diversity and equal opportunity in employment.