Lead Physical Design Engineers

Digicomm Semiconductor INC; Austin, Northern (TX, KY); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Digicomm Semiconductor INC in the United States is seeking a physical design engineer to analyze circuits, partition designs into blocks, and place blocks efficiently across the chip area. The role includes allocating space for external hard IPs and performing PPO before CTS to optimize timing paths.

The position covers clock routing to minimize skew, CTS execution, end-to-end STA timing checks, constraint budgeting, and timing sign-off.

Responsibilities

• Analyze the design and divide into small blocks.
• Split the circuit such that the number of connections between partitions is minimized.
• Identify appropriate places for different blocks within the chip area based on design analysis.
• Allocate places for external hard IPs.
• Perform Post Placement Optimization (PPO) before clock tree synthesis (CTS).
• Route clock signals to minimize clock skew and achieve robust timing.
• Execute Clock Tree Synthesis (CTS).
• Run STA for timing across the complete design and verify timing checks are clean.
• Generate constraints, budgets and timing sign-off.
• Perform IR/EM analysis and ensure signal integrity.
• Conduct layout vs. schematic checks (LVS).
• Carry out Design Rule Checks (DRC) and Electrical Rule Checks (ERC).

Job description

• Analyze the design and divide into small blocks.
• Split the circuit such that the number of connections between partitions is minimized.
• Based on the design analysis identifying appropriate place for different blocks within the chip area.
• Allocating places for external Hard IPs.
• Placing and optimizing the various small blocks identified during partitioning process:
• Post Placement Optimization (PPO) before clock tree synthesis (CTS)
• Routing the various clock signals within the design so that the clock skews are optimized:
• Clock Tree Synthesis (CTS)
• Perform the STA, across the complete design to ensure that all the timing checks are clean:
• Constraint Generation
• Budgeting
• Timing Sign off, IR/EM Analysis
• Signal integrity
• Perform Physical Verification against various critical parameters & criteria:
• Layout Vs Schematic Checks (LVS)
• Design Rule Checks (DRC)
• Electrical Rule Checks (ERC)