Lead Mixed-Signal IC Design Engineer - Hybrid

Anysilicon; San Jose, Northern (CA, KY); Hybrid; USD 150,000 - 190,000; Full time

Job summary

Acacia in San Jose seeks a Mixed Signal Design Engineer to join our IC Design team, blending analog and digital flows to deliver high-speed transceiver products.

You will architect, simulate, and verify ultra-deep sub-micron CMOS designs, mentor peers, and collaborate with packaging and hardware teams to ensure signal integrity.

Hybrid role with three days in-office per week; open until June 30, 2026 or until filled.

Qualifications

• Bachelor's degree with 8 years of related experience, or Master's with 6 years, or PhD with 3 years of related experience.
• Experience in design, simulation, and measurement of high-speed ICs in at least three areas such as high-speed serial links, high-performance output drivers, and equalization techniques.

Responsibilities

• Architect, design, layout, measure, and productize ultra-deep sub-micron-based CMOS products.
• Lead efforts for large blocks on complex chips and mentor team members.
• Participate in peer reviews of complex IC designs and provide solid design methodology from conception to production.
• Collaborate with packaging and hardware design teams to ensure signal and power integrity specifications are met.

Skills

Transceiver applications

FinFET/GAA

High-frequency layout

DFM & validation

Cadence/AMS simulations

Education

Bachelor's degree with 8 years of related experience, or Master's with 6 years, or PhD with 3 years of related experience

Tools

Cadence Virtuoso

Spectre

AMS simulations

Job description

Acacia in San Jose seeks a Mixed Signal Design Engineer to join our IC Design team, blending analog and digital flows to deliver high-speed transceiver products.

You will architect, simulate, and verify ultra-deep sub-micron CMOS designs, mentor peers, and collaborate with packaging and hardware teams to ensure signal integrity.

Hybrid role with three days in-office per week; open until June 30, 2026 or until filled.