Analog & Mixed-Signal IC Design Engineers (2 requisitions)

SiliconBrite Technologies Inc.; San Jose (CA); Hybrid; USD 120,000 - 160,000; Full time

Job summary

A leading IC design firm is seeking seasoned Analog & Mixed-Signal IC Design Engineers in San Jose, CA, or globally remote. Candidates should have over 15 years of experience and a BSEE/MSEE, with significant expertise in analog circuit design and Cadence EDA tools. This role focuses on designing and verifying IP blocks, collaborating with various teams, and supports the full lifecycle of IC products from concept to production.

Qualifications

• 15+ years of direct experience in analog & mixed-signal IC companies.
• Good understanding of the Cadence EDA toolset.
• Strong analytical, verbal, and written communication skills.

Responsibilities

• Design, simulate, and verify various analog IP blocks.
• Work closely with system applications and marketing teams to create new products.
• Support IC design-specific requirements during production phases.

Skills

Analog circuit design

Cadence EDA toolset

Team collaboration

Analytical skills

Education

BSEE/MSEE

Job description

Analog & Mixed-Signal IC Design Engineers (2 requisitions)

Job Id: 2021DE07 , 2021DE08
Location: San Jose, CA or remote

Job Description

Silicon Brite (“SBT”) is seeking two highly motivated and experienced IC design engineer(s) to grow further our design expertise fueled with dynamic company culture to create innovative analog & mixed-signal IC solutions. The designer(s) will perform various proprietary power and analog / mixed-signal (AMS) IC block designs, IP, and products via Cadence EDA tools according to engineering specifications based on various process technologies including but not limited to BCD and BiCMOS processes.

Details

The ideal candidate(s) will further perform

Design, simulate and verify various analog IP blocks including but not limited to A/D Converters, D/A converters, Low Power Bandgap Voltage/Current reference, PLL/Oscillator, PWM Controller, and various other Power Management related IP from individual blocks to full-chip level designs.

Work closely with system applications and technical marketing teams during the definition stage and successfully create new products from concept to tape-out.

Support IC design-specific requirements before, during, and, after volume production phases, including test-to-bench verification with associated test/production teams.

Work with layout engineers to optimize and implement design techniques for in-house developed IP along with the library.

Understanding of physical verification, debug, and parasitic extraction, including LVS/DRC.

Details

The ideal candidate(s) should have the following qualifications

BSEE/MSEE with analog circuit design expertise

15+ years of direct experience working in analog & mixed-signal IC companies

Good understanding of the Cadence EDA toolset

Self-starter and ability to drive for results while taking initiatives with a ‘can-do attitude

Strong analytical, verbal, and written communication skills.

Ability to work in a dynamic team environment; must be a team player

The position can be based in San Jose, CA, or a remote location globally