Lead Low Power Design Engineer: Methodology & Optimization

Google; Austin (TX); On-site; USD 163,000 - 237,000; Full time

Job summary

Google Austin, TX is seeking a Low Power Design Methodology and Optimization Engineer to advance CPU power efficiency across architectures, from design to implementation. You will lead development of power-aware methodologies and collaborate with RTL, synthesis, and physical design teams to deliver optimized silicon.

The role requires deep domain expertise, 8+ years in CPU low power, and experience with UPF/CPF, power modeling, and scripting for design automation.

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CE/CS.
• 8 years of experience in CPU low power design and optimization.
• Experience with power analysis tools, UPF/CPF, and power reduction techniques.
• Experience with RTL design, synthesis, and static timing analysis.

Responsibilities

• Develop and implement advanced low power design methodologies for CPU architectures.
• Perform detailed power analysis, estimation, and optimization across various design stages.
• Collaborate with RTL design, verification, and physical design teams to integrate power-saving features.
• Drive the adoption of innovative power reduction techniques and tools.
• Contribute to the definition and validation of power management specifications.

Skills

RTL design

Synthesis

Static timing analysis

Python

Perl

Power reduction techniques

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science or related field

8 years of experience in CPU low power design and optimization

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science (preferred)

Tools

Power analysis tools

UPF/CPF formats

Job description

Google Austin, TX is seeking a Low Power Design Methodology and Optimization Engineer to advance CPU power efficiency across architectures, from design to implementation. You will lead development of power-aware methodologies and collaborate with RTL, synthesis, and physical design teams to deliver optimized silicon.

The role requires deep domain expertise, 8+ years in CPU low power, and experience with UPF/CPF, power modeling, and scripting for design automation.