Lead High-Speed Interconnect Systems Engineer

MediaTek; Irvine (CA); On-site; USD 188,000 - 301,000; Full time

Benefits offered by this job

Health insurance

Life insurance

Disability insurance

Savings plan

Holidays

Vacation time

Sick leave

Parental leave

401K

Job summary

MediaTek in California seeks an Interconnect Communication System Design Engineer to lead the architecture, modeling, and specification of high-speed interconnect solutions. You will define system-level requirements and develop physical layer algorithms for robust performance under challenging channel conditions across Ethernet and PCIe.

Model algorithms in MATLAB, Python, or C++ for evaluation, optimize for performance, power, area, and latency, and collaborate with global design teams on

Qualifications

• Deep understanding of DSP, error-correction coding, and communication theory.
• Proficiency in MATLAB, Python, or C++ for system modeling.
• Experience with CDR, equalization, compensation, cancellation, sequence detection, and block or convolutional error-correction coding in electrical or optical systems is a plus.
• Experience with analog circuit design or RTL design is a plus.
• Team player with strong communication skills.

Responsibilities

• Develop advanced algorithms and architectures for high-speed electrical/optical wireline communication systems.
• Model the algorithms in MATLAB, Python, or C++ for performance evaluation.
• Optimize algorithms and architectures for performance, power, area, and latency.
• Collaborate with worldwide design teams and provide support for bit-true, cycle-true modeling, design verification, and post-silicon validation.
• Conduct advanced research and development in future wireline communication areas.

Skills

DSP fundamentals

Error-correction coding

Communication theory

RTL/Analog design

Team communication

Education

MS or higher in EE/CS

Tools

MATLAB

Python

C++

Job description

MediaTek in California seeks an Interconnect Communication System Design Engineer to lead the architecture, modeling, and specification of high-speed interconnect solutions. You will define system-level requirements and develop physical layer algorithms for robust performance under challenging channel conditions across Ethernet and PCIe.

Model algorithms in MATLAB, Python, or C++ for evaluation, optimize for performance, power, area, and latency, and collaborate with global design teams on