Lead High-Speed Analog Layout Engineer

Local First Arizona; United States; On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Growth opportunities

Collaborative team culture

Job summary

Celero Communications is seeking a driven High-Speed Analog Layout Engineer to lead the design of complex analog/mixed-signal IP blocks. This role encompasses close collaboration with circuit designers and guidance of junior engineers in an innovative environment.

The ideal candidate will have significant experience in layout design, particularly with FinFET technologies, and a proactive approach to problem-solving. Join Celero to shape the future of AI and data center connectivity in a supportive, collaborative team culture.

Qualifications

• Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies.
• Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes.
• Experience using revision control systems for layout design management.

Responsibilities

• Lead and own the physical layout design of complex analog/mixed-signal macros.
• Collaborate closely with schematic designers to create optimal layout solutions.
• Mentor junior layout engineers/contractors across multiple time zones.

Skills

Analog/Mixed-signal layout design

Leadership

Cadence Virtuoso

Power grid design

Layout verification flows

Tools

Calibre

Pegasus

Job description

Celero Communications is seeking a driven High-Speed Analog Layout Engineer to lead the design of complex analog/mixed-signal IP blocks. This role encompasses close collaboration with circuit designers and guidance of junior engineers in an innovative environment.

The ideal candidate will have significant experience in layout design, particularly with FinFET technologies, and a proactive approach to problem-solving. Join Celero to shape the future of AI and data center connectivity in a supportive, collaborative team culture.