Lead FPGA Design Engineer, Space Avionics

Lanteris Space LLC; San Jose (CA); On-site; USD 123,000 - 251,000; Full time

Benefits offered by this job

Health insurance

401(k)

Paid time off

Job summary

Lanteris Space Systems is seeking an FPGA Design Engineer to join the Bus Electronics Design team in San Jose, CA. This on-site role focuses on avionics hardware development for spacecraft, leading FPGA design for high-speed communications, payload processing, data handling, and sensor interfaces.

Ideal candidates have 8+ years in FPGA design, SystemVerilog/VHDL RTL expertise, and experience with FPGA synthesis, timing closure, and IP integration.

Qualifications

• Bachelor's degree in electrical engineering, computer science, or a related field.
• 8+ years FPGA design experience.
• Proficiency in RTL design, implementation, and simulation in SystemVerilog and/or VHDL.
• Experience configuring hard and soft IP, writing custom IP, and integrating 3rd party IP.

Responsibilities

• Provide technical leadership on FPGA development, from concept through implementation and qualification.
• Lead design, verification, and manufacturing support for avionics hardware.
• Collaborate cross-functionally with hardware and software teams to ensure timely project delivery.
• Ensure high performance, fault-tolerant FPGA designs with timing closure.
• Document engineering tests, qualification plans, and troubleshoot root cause issues.
• Support bench and environmental testing and flight hardware validation.

Skills

FPGA design

SystemVerilog

VHDL

Education

Bachelor's degree in Electrical Engineering or Computer Science

Tools

AMD Xilinx Versal

Microchip RTAX/RTG4

Job description

Lanteris Space Systems is seeking an FPGA Design Engineer to join the Bus Electronics Design team in San Jose, CA. This on-site role focuses on avionics hardware development for spacecraft, leading FPGA design for high-speed communications, payload processing, data handling, and sensor interfaces.

Ideal candidates have 8+ years in FPGA design, SystemVerilog/VHDL RTL expertise, and experience with FPGA synthesis, timing closure, and IP integration.